48
Advanced Chipset features > DRAM Clock/Timing Control > DRAM
Timing Control
Available options:
z
By SPD:
System will define timing according to default of Dram. (Default)
z
Manual:
Allow user to define timing himself.
Advanced Chipset features > DRAM Clock/Timing Control > CAS Latency
Time
When synchronous DRAM is installed, the number of clock cycles of CAS latency
depends on the DRAM timing. Available options:
2
,
2.5, 3
Advanced Chipset features > DRAM Clock/Timing Control > RAS Active
Time
Advanced Chipset features > DRAM Clock/Timing Control > RAS
Precharge Time
If an insufficient number of cycles are allowed for the RAS to accumulate its
charge before DRAM refresh, the refresh may be incomplete and the DRAM may
fail to retain data. Fast give faster performance; and Slow gives more stable
performance. This field applies only when synchronous DRAM is installed in the
system. Available options:
2
,
3, 4, 5
Advanced Chipset features > DRAM Clock/Timing Control > RAS to CAS
Delay
This field lets user to insert a timing delay between the CAS and RAS strobe
signals, used when RAM is written to, read from, or refreshed. Fast gives fater
performance; and Slow give more stable performance. This field applies only
when synchronous DRAM is installed in the system.
Available options:
2
,
3, 4, 5
Advanced Chipset features > Graphic Window WR Combin
Advanced Chipset features > AGP Fast Write Support
Advanced Chipset features > AGP Data Rate
Advanced Chipset features > AGP Aperture Size (MB)
This item allows you to determine the effective size of the AGP Graphic Aperture.
Available options:
4
,
8
,
16
,
32
,
64
,
128
,
256
Advanced Chipset features > Graphics Engin Clock
Advanced Chipset features > VGA Share Memory Size
Advanced Chipset features > Intruder Detection
This item allow user to detect the housing is opened or not. It works only when
the housing is designed with CASE OPEN cable and connected to motherboard.
Available options:
Disabled
,
Enabled
