AOpen DX37PU-OL-E0112B, Руководство пользователя

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F F S S B B ( ( F F r r o o n n t t S S i i d d e e B B u u s s ) ) C C l l o o c c k k
FSB Clock means CPU external bus clock.
CPU internal clock = CPU FSB Clock x CPU Clock Ratio
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See SMBus .
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P1394 (IEEE 1394) is a standard of high-speed serial peripheral bus. Unlike low or medium speed USB , P1394 supports 50 to
1000Mbit/s and can be used for video camera, disk and LAN.
P P a a r r i i t t y y B B i i t t
The parity mode uses 1 parity bit for each byte, normally it is even parity mode, that is, each time the memory data is updated, parity bit
will be adjusted to have even count "1" for each byte. When next time, if memory is read with odd number of "1", the parity error is
occurred and this is called single bit error detection.
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For Socket 7 CPU, one burst data read requires four QWord (Quad-word, 4x16 = 64 bits). PBSRAM only needs one address decoding
time and automatically sends the remaining QWords to CPU according to a predefined sequence. Normally, it is 3-1-1-1, total 6 clocks,
which is faster than asynchronous SRAM. PBSRAM is often used on L2 (level 2) cache of Socket 7 CPU. Slot 1 and Socket 370 CPU
do not need PBSRAM.
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