AMI BIOS Utility
3-16
DRAM WRITE BURST TIMING
This parameter adjusts the write wait state between L2 and DRAM cache. The
L2 cache is processed through write-back method and each cache write
process consists of four continuous cache write cycles. Therefore, it has four
settings to adjust.
The parameter settings are
X444, X333,
and
X222
. Faster DRAMs
require shorter wait states. The value of
X
depends on the DRAM Lead-off
Timing parameter setting.
FAST RAS TO CAS DELAY
This option specifies the wait state between the row address strobe (RAS) and
column address strobe (CAS) signals. The available settings are
3 clocks
and
2 clocks
.
DRAM LEAD-OFF TIMING
This option specifies the DRAM waiting time or the delay before data can be
accessed. Some DRAMs may require a longer delay to access data. The
selections are
11-7-3, 10-6-3, 11-7-4,
and
10-6-4
.
REFRESH RAS# ASSERTION
This function controls the number of clocks required to assert RAS# for refresh
cycles. The available settings are
4 clocks
and
5 clocks
.
FAST EDO PATH SELECT
Enable this option to select a fast path for CPU to DRAM read cycles to
minimize the lead-off time. This is applicable only for EDO DRAMs. For other
DRAM types, we recommend that you set this to
Disabled
.
Содержание AP5V
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