Anaren A110LR09x, Руководство пользователя

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A110LR09x
– User’s Manual
Page 7 of 38
Release Date 10/31/11
accessed through the SPI bus and are implemented as a FIFO register (64 bytes each for Tx
and Rx).
To transmit, a frame of data is placed in the FIFO; this may include a destination address. A
transmit command is given, which will transmit the data according to the initial setup of the
registers. To receive data, a receive command is given, which
enables the unit to “listen” for a
transmission; when such a transmission occurs, it places the received frame in the FIFO. When
neither transmit nor receive is required, the device can enter either an Idle mode, from which it
can quickly re-enter a receive/transmit mode, or a low power sleep mode from which a crystal
startup is required prior to transmit or receive operation.
Below is a block diagram for each of the A110LR09A and A110LR09C modules.

Antenna
o
The antenna couples energy between the air and the AIR module. For
applications where installations are done by an end user (non-professional), an
omni-directional antenna pattern is desired such that the application will work
equally well in every direction. Similarly for peer to peer or point to multipoint
applications, an omni-directional pattern is desired such that all nodes have a fair
chance of communicating. The A110LR09A module has an integral antenna that
is near omni-directional, whereas the A110LR09C has approved antenna options
ranging from near omni-directional to shaped front/back patterns (useful for
inline, professional installations). Note that the end radiation pattern depends not
only on the antenna, but also on the ground plane, enclosure and installation
environment.

Filtering
o
Filtering removes spurious signals to comply with regulatory intentional radiator
requirements.

Matching
o
Matching provides the correct loading of the transmit amplifier to achieve the
highest output power, as well as the correct loading for the receive LNA to
achieve the best sensitivity.

Physical
o
The physical layer provides conversions between data, symbol and RF signal.

MAC
o
The MAC layer is part of the Logical Link Layer and provides frame handling,
addressing and medium access services. For CE operations, part of the MAC is
implemented in the S/W.

Microcontroller Interface
o
The microcontroller interface exposes registers and commands for the physical
and MAC layers to a microcontroller.

Power Management
o
Power management ensures a stable supply for the internal functions, as well as
providing means for a low power sleep mode (in which case, most of the
transceiver is power off).