ADSP-TS201S
Rev. C
|
Page 27 of 48
|
December 2006
Table 27. Normal Reset Timing
Parameter
Min
Max
Unit
Timing Requirements
t
RST_IN
RST_IN Asserted
2
ms
t
STRAP
RST_IN Deasserted After Strap Pins Stable
1.5
ms
Switching Characteristic
t
RST_OUT
RST_OUT Deasserted After RST_IN Deasserted
1.5
ms
Figure 14. Normal Reset Timing
Table 28. On-Chip DRAM Refresh
1
Parameter
Min
Max
Unit
Timing Requirement
t
REF
On-chip DRAM Refresh Period
1.56
μ
s
1
For more information on setting the refresh rate for the on-chip DRAM, refer to the
ADSP-TS201 TigerSHARC Processor Programming Reference
.
STRAP PINS
t
STRAP
RST_IN
t
RST_IN
RST_OUT
t
RST_OUT
Содержание TigerSHARC ADSP-TS201S
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