UG-934
EVAL-SSM3582Z User Guide
Rev. 0 | Page 6 of 13
EVALUATION BOARD SCHEMATICS AND ARTWORK
T O S S M 3 5 8 2
T O S S M 3 5 8 2
T O S PD I F R X
E X T S U PPLY
PV D D I N PU T
ADDR1
ADDR0
SCL_ 3 5 8 2
SDA_ 3 5 8 2
FSYNC_ 3 5 8 2
SDATA_ 3 5 8 2
BCLK_ 3 5 8 2
OUTL–
OUTL+
OUTR+
OUTR–
SSM3 5 8 2
SHEET- 2
SDA_ 3 5 8 2
OMCK_ I N
SCL_ 3 5 8 2
SDATA_ 3 5 8 2
FSYNC_ 3 5 8 2
BCLK_ 3 5 8 2
8 4 1 6 _ MCLK
ADDR0
ADDR1
I 2 S_ I 2 C
SHEET-3
PVDD
+ 3 V3
+ 1 V8
+ 5 V
+ 5 V_ EXT
+ 3 V3 _ EXT
+ 1 V8 _ EXT
POWER_SUPPLY
SHEET- 4
OUTL+
OUTL-
OUTR+
OUTR–
OUTPUTS
SHEET- 5
14262-
006
Figure 6. Schematic of the
SSM3582
Evaluation Board Block Diagram
C 2 6
0 . 1 0 µ F
C1 9
0 . 1 0 µ F
1
2
J2 3
2 - JUMPER
1
2
J1 7
TP3 0
TP2 9
TP2 8
TP2 7
TP2 5
TP2 6
TP2 4
TP2 3
TP9
TP8
TP7
TP6
TP5
TP4
TP3
TP2
TP2 2
TP2 1
TP1
T
P
1
2
T
P
1
4
T
P
1
8
TP1 0
1
PGND
2
PGND
3
AVDD_EN
4
SCL
5
SDA
6
FSYNC
7
SDATA
8
BCLK
9
PGND
1 0
PGND
1
1
B
S
T
R
+
1
2
O
U
T
R
+
1
3
O
U
T
R
+
1
4
P
V
D
D
1
5
P
V
D
D
1
6
P
V
D
D
1
7
P
V
D
D
1
8
O
U
T
R
–
1
9
O
U
T
R
–
2
0
B
S
T
R
–
2 1
PGND
2 2
PGND
2 3
DVDD_EN
2 4
AVDD
2 5
AGND
2 6
ADDR0
2 7
ADDR1
2 8
DVDD
2 9
PGND
3 0
PGND
3
1
B
S
T
L
–
3
2
O
U
T
L
–
3
3
O
U
T
L
–
3
4
P
V
D
D
3
5
P
V
D
D
3
6
P
V
D
D
3
7
P
V
D
D
3
8
O
U
T
L
+
3
9
O
U
T
L
+
4
0
B
S
T
L
+
4
1
E
P
A
D
U5
SSM3 5 8 2
C1 4
0 . 2 2 µ F
C1 6
0 . 2 2 µ F
C1 3
1 0 µ F
C1 7
1 0 µ F
C2 9
1 0 µ F
C3 7
1 0 µ F
C3 1
0 . 2 2 µ F
C3 3
0 . 2 2 µ F
T
P
3
8
T
P
3
4
T
P
3
2
R
1
7
4
7
k
Ω
C1 5
0 . 1 0 µ F
C3 2
0 . 1 0 µ F
A
B
1
2
3
J
P
8
J
U
M
P
E
R
2
S
IP
3
A
B
1
2
3
J
P
9
J
U
M
P
E
R
2
S
IP
3
C4 3
1 0 pF
C4 4
1 0 pF
C4 5
1 0 pF
+ 1 V8
AVDD_ 3 5 8 2
DVDD_ 3 5 8 2
ADDR1
ADDR0
AVDD_ 3 5 8 2
LDO_ 1 V8 _ EN
PVDD
PVDD
PVDD
PVDD
SCL_ 3 5 8 2
GND
GND
GND
GND
GND
SCL_ 3 5 8 2
SDA_ 3 5 8 2
FSYNC_ 3 5 8 2
SDATA_ 3 5 8 2
BCLK_ 3 5 8 2
O
U
T
L
–
O
U
T
L
+
O
U
T
R
+
O
U
T
R
–
+5V
AV D D _ 3 5 8 2
PV D D
AV D D _ 3 5 8 2
AD D R0
AD D R1
LDO_ 5 V_ EN
S D A_ 3 5 8 2
BCLK_ 3 5 8 2
S D ATA_ 3 5 8 2
FS YN C_ 3 5 8 2
14262-
007
Figure 7. Schematic of the
SSM3582
Evaluation Board,
SSM3582
Section
