background image

EVAL-SSM2317-MINI 

 

Rev. 0 | Page 4 of 8 

PCB LAYOUT GUIDELINES 

To keep the EMI under the allowable limit and ensure that the 
amplifier chip operates under the temperature limit, PCB layout 
is critical in application design. The SSM2317 works well only if 
the following techniques are implemented in the PCB design to 
keep EMI and the amplifier temperature low. 

Layer Stacks and Grounding 

Use a 4-layer structure in the stack-up for the evaluation board, 
as follows: 

 

Top layer—component layer with power and output copper 
land and ground copper pouring. 

 

Second layer—dedicated ground plane. 

 

Third layer—dedicated power plane. 

 

Bottom layer—bottom layer with ground copper pouring. 

Component Placement and Clearance 

Place all related components except decoupling capacitors on 
the same side as the SSM2317 to avoid vias and as close as 
possible to the chip (see Figure 4). 

Place the decoupling capacitors, C5 and C7, on the bottom side 
as close as possible to the VDD and GND pins (see Figure 5). 

Place the C3 and C4 capacitors and the R1 pull-up resistor on 
the bottom layer (see Figure 5). 

Traces and Solder Resist 

All traces between adjacent pads must be covered with solder 
resist. Traces should come symmetrically off the pads. 

Use 5 mils traces at the SSM2317 pads to prevent the solder 
from escaping. 

Top Layer Copper Land and Ground Pouring  

The output peak current of this amplifier is more than 1 A; 
therefore, PCB traces should be wide (>2 mm) to handle high 
current. For the best performance, use symmetrical copper 
lands as large as space allows, instead of traces for output pins 
(see Figure 3).  

Pour ground copper on the top side and use many vias to 
connect the top layer ground copper to the dedicated ground 
plane. The copper pouring land on the top layer serves as both 
the EMI shielding ground plane and the heat sink for the 
SSM2317. 

Power Land 

Connect Pin B2 directly to Pin A2 by a 5 mil trace and make a 
copper land for the power near A2. If space allows, use four 
12/24 mil vias to connect the top layer power land to the 
dedicated power plane (Layer 3).  

GETTING STARTED 

To ensure proper operation, carefully follow Step 1 through Step 3. 

1.

 

Connect the load to the audio output terminals, OUT+ and 
OUT−. 

2.

 

Connect the audio input to the audio input terminals, IN+ 
and IN−. 

3.

 

Connect the power supply to VDD and GND. 

 

 

Содержание EVAL-SSM2317-MINI

Страница 1: ...less than 1 THD N driving an 8 Ω load from a single 5 0 V supply The SSM2317 is equipped with a differential mode input port and a high efficiency full H bridge at the output that enables direct coupling of the audio power signal to the loudspeaker The differential mode input stage allows for cancelling of common mode noise The part also features a high efficiency low noise output modulation schem...

Страница 2: ...ion 1 Revision History 2 Evaluation Board Hardware 3 Input and Output Configuration 3 Component Selection 3 PCB Layout Guidelines 4 Getting Started 4 Evaluation Board Schematic and Artwork 5 Ordering Information 8 Bill of Materials 8 Ordering Guide 8 ESD Caution 8 REVISION HISTORY 5 09 Revision 0 Initial Version ...

Страница 3: ...incoming signal but small enough to filter out unnecessary lower frequency signals For music signals the cutoff frequency is typically between 20 Hz and 30 Hz The cutoff frequency is calculated by C 1 2πRfc where R 10 kΩ Rext the external resistor used to fine tune the desired gain on the schematics see Figure 3 this is the 0 Ω resistor at the input pins fc is the cutoff frequency Output Ferrite B...

Страница 4: ...ottom layer see Figure 5 Traces and Solder Resist All traces between adjacent pads must be covered with solder resist Traces should come symmetrically off the pads Use 5 mils traces at the SSM2317 pads to prevent the solder from escaping Top Layer Copper Land and Ground Pouring The output peak current of this amplifier is more than 1 A therefore PCB traces should be wide 2 mm to handle high curren...

Страница 5: ...4 003 IN OUT IN 1B 1A IN IN P1 P2 3C OUT OUT 3B OUT SD GND ALC_EN VTH 2A 2B 3A VDD 1C 2C U1 SSM2317 C1 0 1µF C3 1nF C4 1nF C2 0 1µF R3 6 98kΩ G1 GAP R2 100kΩ R1 100kΩ VDD VDD C7 0 1µF C5 10µF P1 P6 VDD P3 P4 L1 B0603 L2 B0603 Figure 3 Schematic of the SSM2317 MINI Evaluation Board ...

Страница 6: ... 004 Figure 4 Top Layer with Top Silkscreen 07824 005 Figure 5 Bottom Layer with Bottom Silkscreen Mirror Image 07824 006 Figure 6 Top Silkscreen 07824 007 Figure 7 Top Layer 07824 008 Figure 8 Top Layer 07824 009 Figure 9 Layer 2 Ground Plane ...

Страница 7: ...EVAL SSM2317 MINI Rev 0 Page 7 of 8 07824 010 Figure 10 Layer 3 Power Plane 07824 011 Figure 11 Bottom Layer 07824 012 Figure 12 All Layer Silkscreen ...

Страница 8: ... Murata GRM31MF51A106ZA01L 1 G1 GAP N A 2 L1 L2 Ferrite chip B0603 220 Ω 2 A TDK MPZ1608S221A 6 P1 P2 P3 P4 P5 P6 PAD1 N A 2 R1 R2 Resistor 100 kΩ Panasonic ERJ 1GEF1003C 1 R3 Resistor 6 98 kΩ Panasonic ERJ 1GEF6981C 1 U1 SSM2317 Analog Devices SSM2317 ORDERING GUIDE Model Description SSM2317 MINI EVALZ1 Evaluation Board 1 Z RoHS Compliant Part ESD CAUTION 2009 Analog Devices Inc All rights reserv...

Отзывы: