Analog Devices EVAL-ADP5020, Руководство пользователя, Страница: 9 / 24

EVAL-ADP5020
Rev. 0 | Page 9 of 24
The LDO Vout Selection drop-down box allows you to change
the LDO regulator output voltage to one of the following settings:
1.8 V, 1.9 V, 2.0 V, 2.1 V, 2.2 V, 2.3 V, 2.4 V, 2.5 V, 2.6 V, 2.7 V, 2.8 V,
2.9 V, 3.0 V, 3.1 V, 3.2 V, or 3.3 V. The default value is 1.8 V. This
box corresponds to LDO_VSEL, Bits[3:0] in the BUCK2_
LDO_VSEL register (Address 0x02).
The Buck 1 Control check box activates, if selected, or deactivates,
if cleared, the Buck 1 regulator. This check box corresponds to
BK1_EN, Bit[7] in the REG_CONTROL_STATUS register
(Address 0x03).
The Buck 2 Control check box activates, if selected, or deactivates,
if cleared, the Buck 2 regulator. This check box corresponds to
BK2_EN, Bit[6] in the REG_CONTROL_STATUS register
(Address 0x03).
The LDO Control check box activates, if selected, or deactivates,
if cleared, the LDO regulator. This check box corresponds to
LDO_EN, Bit[5] in the REG_CONTROL_STATUS register
(Address 0x03).
The Enable All Regulators check box activates, if selected, or
deactivates, if cleared, all regulators available. This check box
corresponds to EN_ALL, Bit[4] in the REG_CONTROL_STATUS
register (Address 0x03).
The XSHTDWN on Buck 1 check box allows you to mask the
Buck 1 power-good (PGOOD) signal, if selected, or to control
the power-good signal, if cleared, to generate the XSHTDWN
signal. This check box corresponds to BK1_XSHTDN, Bit[3] in
the OPERATIONAL_CONTROL register (Address 0x04).
The XSHTDWN on Buck 2 check box allows you to mask the
Buck 2 power-good (PGOOD) signal, if selected, or to control
the power-good signal, if cleared, to generate the XSHTDWN
signal. This check box corresponds to BK2_XSHTDN, Bit[2] in
the OPERATIONAL_CONTROL register (Address 0x04).
The XSHTDWN on LDO check box allows you to mask the
LDO power-good (PGOOD) signal, if selected, or to control
the power-good signal, if cleared, to generate the XSHTDWN
signal. This check box corresponds to LDO_XSHTDN, Bit[1]
in the OPERATIONAL_CONTROL register (Address 0x04).
The Force XSHTDWN check box, if cleared, forces the XSHTDN
pin level to Logic 0; if selected, the XSHTDN logic level depends
on the power-good (PGOOD) status of the regulators. This check
box corresponds to FORCE_XS, Bit[0] in the REG_CONTROL_
STATUS register (Address 0x03).
The Buck 1 PGOOD check box shows the power-good status
for the Buck 1 regulator. If the check box is selected, the Buck 1
regulator is operating correctly; if cleared, it indicates that the
Buck 1 regulator is either not activated or in a failing condition.
This check box corresponds to BK1_PGOOD, Bit[3] in the
REG_CONTROL_STATUS register (Address 0x03).
The Buck 2 PGOOD check box shows the power-good status
for the Buck 2 regulator. If the check box is selected, the Buck 2
regulator is operating correctly; if cleared, it indicates that the
Buck 2 regulator is either not activated or in a failing condition.
This check box corresponds to BK2_PGOOD, Bit[2] in the
REG_CONTROL_STATUS register (Address 0x03).
The LDO PGOOD check box shows the power-good status for
the LDO regulator. If the check box is selected, the LDO regula-
tor is operating correctly; if cleared, it indicates that the LDO
regulator is either not activated or in a failing condition. This
indicator corresponds to LDO_PGOOD, Bit[1] in the REG_
CONTROL_STATUS register (Address 0x03).
The Thermal Shutdown check box shows the status for the
thermal shutdown (TSD) protection. If the check box is selected,
the device is in a TSD condition; if cleared, it indicates that the
device is operating normally. This check box corresponds to TSD,
Bit[0] in the OPERATIONAL_CONTROL register (Address 0x04).
When this check box is selected (set to 1), you must clear this
check box, then write this bit back to the device to clear a TSD
condition. Make sure to clear the
Regs Refresh check box to
override this indicator. If the Regs Refresh option is enabled
(check box is selected), the periodic refresh writes back the TSD
indicator and you will not be able to clear the TSD bit. You must
not write this indicator (that is, you must not click the
Write
Registers button ) while the Thermal Shutdown check box is
selected (set to 1) because this forces a TSD condition and the
regulators, if enabled, stops working.
The EN/GPIO Options drop-down box allows you to program
the function associated with the EN/GPIO pin to one of the follow-
ing settings: input high impedance, output low, or output high.
This box corresponds to ENO_DRV, Bit[0], and ENO_HIZ_BAR,
Bit[1], in the EN_CONTROL register (Address 0x05).
The SYNC Options drop-down box allows you to program the
function associated with the SYNC pin to one of the following
settings: internal clock, external dc-coupled 9.6 MHz clock,
external dc-coupled 19.2 MHz clock, external ac-coupled
9.6 MHz clock, or external ac-coupled 19.2 MHz clock. This
box corresponds to SYNC_9P6, Bit[6], and SYNC_19P2, Bit[5],
in the OPERATIONAL_CONTROL register (Address 0x04).
The DEVICE REVISION box shows the major and minor
revision, and the specific device option. It is not possible to alter
the values in this box because it is a hard-coded value in the
device. This box corresponds to MAJ, Bits[7:5], MIN, Bits[4:2],
and OPT, Bits[1:0], in the revision register (Address 0x00).
To read or write the device register in bit or byte format as
shown in the device memory map (see the ADP5020 data
sheet), you can open the registers map utility by clicking the
Registers MAP button. See the Registers Commands section
for additional information.