UG-916
EVAL-ADM2582EEMIZ/EVAL-ADM2587EEMIZ User Guide
Rev. 0 | Page 4 of 12
TERMINATION AND PULL-UP/PULL-DOWN
RESISTORS
The evaluation board includes the RT and RT1 footprints for
fitting termination resistors between the A and B receiver inputs
and the Y and Z driver outputs. By default, the board is not
fitted with a 120 Ω resistor, RT, between A and B. This resistor
must be removed if the board is connected to a bus that is
already terminated at both ends. For more information about
proper termination, see the
AN-960 Application Note
,
RS-
485/RS-422 Circuit Implementation Guide
.
Although the
ADM2582E
/
ADM2587E
have a built-in receiver
fail-safe for the bus idle condition, there are footprints on the
evaluation board for fitting the R9 and R10 pull-up resistors to
the V
ISOOUT
supply of the ADM2582E/ADM2587E on A and Y,
as well as the R7 and R8 pull-down resistors to GND
2
on B and Z.
These resistors can be fitted if the user is connecting to other
devices that require external biasing resistors on the bus. The
exact value required for a 200 mV minimum differential voltage
in the bus idle condition depends on the supply voltage (for
example, 960 Ω for 3.3 V and 1440 Ω for 5 V).
For more information about the bus idle fail-safe, see the
AN-960
Application Note
,
RS-485/RS-422 Circuit Implementation Guide
.
DECOUPLING AND RESERVOIR CAPACITORS
The evaluation board uses the following decoupling and
reservoir capacitors:
•
On the logic side of the board, the C3 and C4 capacitors
must be 10 nF and 100 nF ceramic capacitors, respectively,
and the C2 capacitor must be a 10 µF tantalum capacitor.
•
On the logic side of the board, the C7 capacitor must be a
100 nF ceramic capacitor, and the C9 capacitor must be a
10 µF tantalum capacitor.
•
On the logic side of the board additional capacitors are
added for the power regulation circuits. C12, C13, and C16
must be a 10 µF tantalum capacitors, while C14 and C15
must be 100 nF ceramic capacitors.
•
On the bus side of the board, the C5 and C6 capacitors
must be 10 nF and 100 nF, respectively, and the C1 and
C98 capacitors must be 100 nF and 10 µF, respectively.
BOARD INTERNAL LAYER THICKNESS
The
ADM2582E
/
ADM2587E
evaluation board consists of two
layers. The spacing between the top and bottom layer is 1.6 mm.
The
EVAL-ADM2582EEMIZ
and
EVAL-ADM2587EEMIZ
PCB
has a layer spacing of 0.4 mm between Layer 1 and Layer 2,
meeting requirements for isolation standards IEC 61010, third
edition, and IEC 60950 in the
AN-1109 Application Note
,
Recommendations for Control of Radiated Emissions with iCoupler
Devices
.
PCB LAYOUT RECCOMENDATIONS
The
ADM2582E
/
ADM2587E
evaluation board is designed to
reduce emissions generated by the high frequency switching
elements used by the
iso
Power technology to transfer power
through the
ADM2582E
/
ADM2587E
integrated transformer.
The layout of the evaluation board is generated using the
guidelines provided in the
AN-1349 Application Note
.
The
AN-1349 Application Note
provides examples of 4-layer PCBs.
The
EVAL-ADM2582EEMIZ
and
EVAL-ADM2587EEMIZ
PCB
layout is a 2-layer PCB. To pass EN55022 Class A on a 2-layer
PCB, the following layout guidelines are recommended:
•
Ensure that there is good decoupling on the PCB (see the
Decoupling and Reservoir Capacitors section).
•
Place a ferrite bead between the PCB trace connections and
the following IC pins: V
ISOOUT
(Pin 12) and GND
2
(Pin 11
and Pin 14).
•
Do not connect the V
ISOOUT
pin to a power plane;
connect between V
ISOOUT
and V
ISOIN
using a PCB trace.
Ensure V
ISOIN
(Pin 19) is connected through the L3 ferrite
to V
ISOOUT
(Pin 12) as shown in Figure 3.
•
Place a high voltage discrete capacitor connected between
GND
1
(Pin 10) and GND
2
(Pin 11).The
EVAL-
ADM2582EEMIZ
requires a high voltage discrete capacitor
in order to pass EN 55022 Class A with adequate margin to
allow for test variation. However, the
EVAL-ADM2587EEMIZ
can pass EN 55022 Class A without a high voltage discrete
capacitor. Adding a high voltage discrete capacitor to the
EVAL-ADM2587EEMIZ
allows a larger pass margin from
the EN55022 Class A limits.
The following additional notes apply to the PCB layout; refer to
the schematic and artwork in Figure 10 to Figure 13.
•
Ensure GND
2
(Pin 14) is connected to GND
2
(Pin 11) on
the inside (device side) of the C1 100 nF capacitor.
•
Ensure the C1 capacitor is connected between V
ISOOUT
(Pin 12) and GND
2
(Pin 11) on the device side of the L2
and L3 ferrites.
•
Ensure GND
2
(Pin 16) is connected to GND
2
(Pin 11) on
the outside (bus side) of the L2 ferrite as shown in Figure 3.
•
Ensure that there is a keep out area for the GND
2
plane in
the PCB layout around the L2 and L3 ferrites. The keep
out area means there must not be a GND
2
fill on any layer
below the L2 and L3 ferrites.
•
Ensure there is a minimum of 4 mm separation gap
between the GND
2
plane fill and the GND
2
fill for the C19
high voltage discrete capacitor pad.
