Analog Devices EVAL-ADAU1860, Руководство пользователя

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User Guide EVAL-ADAU1860
SETTING UP COMMUNICATION IN SOFTWARE
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Figure 4. Connect with EVAL-ADAU1860EBZ
Configure the Register Control , FastDSP , and EQ settings on
the left navigation panel. Lark Register Control has multiple tabs
that control different sections of the ADAU1860 . Figure 5 shows
the Power tab, which allows the user to power up or power down
various blocks within the ADAU1860. When a block is powered up,
that block can be configured.
The Clock tab allows the phase-locked loop (PLL) to be used or
bypassed. By register default, the PLL is disabled to save power.
To generate a 24.576 MHz master clock, enable or disable the PLL
according to the provided clock source. On the evaluation board,
a 24.576 MHz oscillator and a crystal with same frequency are
supplied. To configure an application, follow these steps:
1. Select Hibernate1 , BLOCKS_ON , and CM_BST_ON in the
CHIP_PWR block in the Power tab, and then click Write (see
Figure 5 ).
2. With the default 24.576 MHz oscillator on board, select
MCLK_FREQ_24P576 of MCLK_FREQ_INDEX and set
PLL_FM_BYPASS to PLL_FM_BP in the Clock tab, then click
on Write .
3. Configure the other blocks.
When a register value is changed, click the related Write button in
a block to update a single register, or the Write this Page button
below the tabs to update multiple registers. Click Write All after all
register changes to avoid a configuration error.