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User Guide

EVAL-ADAU1860

SETTING UP THE EVALUATION BOARD

analog.com

Rev. 0 | 4 of 26

INSTALLING THE LARK STUDIO SOFTWARE

Download and install the latest version of 

Lark Studio

 by completing

the following steps:

1.

Download the installer and run the executable file.

2.

Follow the prompts, including accepting the license agreement,

to install the software.

INSTALLING THE USB DRIVERS

If the USB interface is not recognized by the Lark Studio software

and PC, go to the Future Technology Devices International (FTDI)

Chip official web page and download the relevant drivers.

DEFAULT SWITCH AND JUMPER SETTINGS

Table 1

 shows the default switch and jumper settings.

Table 1. Default Switch and Jumper Settings
Jumper and Switch Connections

Option Selected

Pin 1 to Pin 2 of P17

AVDD and HPVDD supplied by 1.8 V on-board low dropout (LDO) regulator

Pin 1 to Pin 2 of P48 and JP3 Removed

IOVDD supplied by 1.8 V on-board LDO

Pin 1 to Pin 2 of P19 and JP2 Connected

HPVDD_L supplied by 1.3 V on-board LDO

Pin 1 to Pin 2 of P18 and JP1 Connected

DVDD supplied by 0.9 V on-board LDO

Pin 2 to Pin 3 of P26

Self boot disabled

Pin 2 to Pin 3 of P24

REG_EN disabled

Pin 2 to Pin 3 of P29

ROM boot disabled

S1 Down (SPI), Pin 2 to Pin 3 of P1, Pin 2 to Pin 3 of P4, Pin 2 to Pin 3 of P5, and
Pin 2 to Pin 3 of P6

SPI communication

Pin 1 of S14 to GND and Pin 2 of S14 to GND

I

2

C Address 0x64

Pin 1 to Pin 2 of P8 and Pin 2 to Pin 3 of P27 to P27

The master clock source is the on-board, 24.576 MHz oscillator

Pin 1 to Pin 2 of P104 and Pin 1 to Pin 2 of P105

ADC0 differential mode

Pin 1 to Pin 2 of P12 and Pin 1 to Pin 2 of P14

ADC1 differential mode

Pin 1 to Pin 2 of P13 and Pin 1 to Pin 2 of P15

ADC2 differential mode

Содержание EVAL-ADAU1860

Страница 1: ...tion users can communicate and debug with the Tensilica HiFi 3z DSP core through the JTAG port by using the mIDAS Link emulator The software development kit SDK is also provided by Analog Devices for...

Страница 2: ...4 Default Switch and Jumper Settings 4 Setting Up Communication in Software 5 Powering Up the Evaluation Board 5 Connecting the Audio Cables 5 Creating a Basic Signal Flow 5 Using the Evaluation Boar...

Страница 3: ...User Guide EVAL ADAU1860 EVALUATION BOARD BLOCK DIAGRAM analog com Rev 0 3 of 26 Figure 2 EVAL ADAU1860EBZ Board Block Diagram...

Страница 4: ...to Pin 2 of P17 AVDD and HPVDD supplied by 1 8 V on board low dropout LDO regulator Pin 1 to Pin 2 of P48 and JP3 Removed IOVDD supplied by 1 8 V on board LDO Pin 1 to Pin 2 of P19 and JP2 Connected H...

Страница 5: ...a basic signal flow in LARK Studio follow these steps 1 Download and install Lark Studio from www ana log com ADAU1860 2 Start Lark Studio by double clicking the shortcut on the desktop 3 Click New P...

Страница 6: ...ate a 24 576 MHz master clock enable or disable the PLL according to the provided clock source On the evaluation board a 24 576 MHz oscillator and a crystal with same frequency are supplied To configu...

Страница 7: ...d finishes FastDSP is enabled and runs automatically If the equalizer is required in the project a configuration of the filters must be set for the ADAU1860 as follows 1 Click on EQ in the navigation...

Страница 8: ...User Guide EVAL ADAU1860 SETTING UP COMMUNICATION IN SOFTWARE analog com Rev 0 8 of 26 Figure 6 FastDSP Schematic Configuration...

Страница 9: ...O regulator with a 3 3 V output Table 2 Power Supply Jumper Setting Power Source On Board LDO Regulator External Jumper Settings Power Supply Voltage V Jumper Settings Port AVDD and HPVDD Pin 1 to Pin...

Страница 10: ...able 3 Control Port Jumper and Switch S1 Settings Communication Port Address Setting Jumper Settings Switch Settings SPI Not applicable Pin 2 to Pin 3 of P1 Pin 2 to Pin 3 of P4 Pin 2 to Pin 3 of P5 a...

Страница 11: ...line inputs and all of the inputs are differential or single ended Each analog input can work with an optional programmable gain amplifier PGA Refer to Table 5 for the hardware configuration of the a...

Страница 12: ...k Pin 8 of P2 MP0 Pin 10 of P2 I2S1 Data Out Pin 2 of P3 I2S1 Data In Pin 4 of P3 I2S1 Frame Clock Pin 6 of P3 I2S1 Bit Clock Pin 8 of P3 External MCLK Input Pin 10 of P3 OTHER INTERFACES Other interf...

Страница 13: ...o select single ended input or differential input AINP2 connects to GND P14 ADC1 input option Used to select single ended input or differential input AINP1 connects to CM P15 ADC2 input option Used to...

Страница 14: ...pin jumper Used to connect the CLK pin on the on board flash to the MP11 pin on the ADAU1860 P51 to P54 and P55 to P58 Flash jumper Used to connect ADAU1860 pins to the on board flash Connected P55 t...

Страница 15: ...User Guide EVAL ADAU1860 EVALUATION BOARD SCHEMATICS AND ARTWORK analog com Rev 0 15 of 26 Figure 7 EVAL ADAU1860EBZ Schematics Page 1...

Страница 16: ...User Guide EVAL ADAU1860 EVALUATION BOARD SCHEMATICS AND ARTWORK analog com Rev 0 16 of 26 Figure 8 EVAL ADAU1860EBZ Schematics Page 2...

Страница 17: ...User Guide EVAL ADAU1860 EVALUATION BOARD SCHEMATICS AND ARTWORK analog com Rev 0 17 of 26 Figure 9 EVAL ADAU1860EBZ Schematics Page 3...

Страница 18: ...User Guide EVAL ADAU1860 EVALUATION BOARD SCHEMATICS AND ARTWORK analog com Rev 0 18 of 26 Figure 10 EVAL ADAU1860EBZ Schematics Page 4...

Страница 19: ...User Guide EVAL ADAU1860 EVALUATION BOARD SCHEMATICS AND ARTWORK analog com Rev 0 19 of 26 Figure 11 EVAL ADAU1860EBZ Schematics Page 5...

Страница 20: ...User Guide EVAL ADAU1860 EVALUATION BOARD SCHEMATICS AND ARTWORK analog com Rev 0 20 of 26 Figure 12 EVAL ADAU1860EBZ Schematics Page 6...

Страница 21: ...User Guide EVAL ADAU1860 EVALUATION BOARD SCHEMATICS AND ARTWORK analog com Rev 0 21 of 26 Figure 13 EVAL ADAU1860EBZ Schematics Page 7 Figure 14 EVAL ADAU1860EBZ Schematics Page 8...

Страница 22: ...User Guide EVAL ADAU1860 EVALUATION BOARD SCHEMATICS AND ARTWORK analog com Rev 0 22 of 26 Figure 15 EVAL ADAU1860EBZ Schematics Page 9...

Страница 23: ...SCHEMATICS AND ARTWORK analog com Rev 0 23 of 26 Figure 16 EVAL ADAU1860EBZ Layer 1 Component Side Figure 17 EVAL ADAU1860EBZ Layer 2 Ground Plane Figure 18 EVAL ADAU1860EBZ Layer 3 Power Plane Figur...

Страница 24: ...10 X7R 0603 AEC Q200 low equivalent series resistance ESR TDK CGA3E1X7R1C105 K080AC 2 C65 and C67 27 pF ceramic capacitors 50 V 5 C0G 0603 PHYCOMP Yageo AC0603JRNPO9BN 270 2 C66 and C68 4 7 F ceramic...

Страница 25: ...slide 4 pole double throw TE Connectivity MSS420004 23 S2 to S13 and S15 to S25 Switches tactile 6 mm Gullwing surface mounted device SMD TE Connectivity LTD FSM6JSMA 1 S14 Single position single thro...

Страница 26: ...er shall inform ADI of any occurred damages or any modifications or alterations it makes to the Evaluation Board including but not limited to soldering or any other activity that affects the material...

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