Analog Devices EVAL-AD7625FMCZ, Руководство пользователя

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UG-745 EVAL-AD7625FMCZ/EVAL-AD7626FMCZ User Guide
Rev. A | Page 4 of 28
EVALUATION BOARD HARDWARE
DEVICE DESCRIPTION
The AD7625 / AD7626 are 6 MSPS/10 MSPS, high precision,
power efficient, 16-bit PulSAR ADCs that use SAR based
architecture and do not exhibit any pipeline delay or latency.
The
AD7625 / AD7626 are specified for use with 5 V and 2.5 V
supplies (VDD1, VDD2). The interfaces from the digital host to
the
AD7625 / AD7626 use 2.5 V logic only.
The AD7625 / AD7626 use an LVDS interface to transfer data
conversions. Complete specifications for the AD7625 / AD7626
are provided in the respective product data sheets, which should
be consulted in conjunction with this user guide when using the
EVAL-AD7625FMCZ / EVAL-AD7626FMCZ evaluation boards.
Full details on the EVAL-SDP-CH1Z are available at the SDP
product page on the Analog Devices website.
HARDWARE LINK OPTIONS
The default link settings on the board and the function of the
link options are described in Table 1.
POWER SUPPLIES
The power (12 V) for the EVAL-AD7625FMCZ / EVAL-
AD7626FMCZ evaluation boards comes through a 160-pin
FMC connector (J7) from the EVAL-SDP-CH1Z SDP board.
The user also has the option of using external bench top supplies
to power the on-board amplifiers. The on-board regulators
generate the required levels from the applied 12 V rail.
The
ADP7102 (U18) supplies 7 V for the +V
S
of the ADC driver
amplifiers ( ADA4899-1 or ADA4932-1 ) and the external reference
ADR4540 (U14). The ADP7104 (U10) delivers 5 V for VDD1
(U1), the external reference ADR3412 (U4), the ADP2300 (U5),
and the ADP124 (U12 and U16). The ADP2300 (U5) generates
−2.5 V for the amplifier –V
S
. The ADP124 (U12 and U16) provides
a 2.5 V supply for VDD2 and VIO (U1).
The 3.3 V supply for the EEPROM (U7) comes from the
EVAL-
SDP-CH1Z through a 160-pin FMC connector (J7). Each supply
is decoupled where it enters the board and again at each device.
A single ground plane is used on this board to minimize the
effect of high frequency noise interference.
Table 1. Pin Jumper Descriptions
Link Default Description
JP1, JP2 B to center Connects CNV+ and CNV− from the FPGA. The A to center position connects the CNV signal from the AD9513 .
JP6 B to center Connects 7 V to ampV
S
.
JP10 B to center Connects −2.5 V to amplifier −V
S
.
JP11, JP12 B to center Connects analog inputs VIN+ and VIN− to the inputs of the ADC driver ADA4899-1 or ADA4897-1 . The A to
center position sets the fully differential path through the ADA4932-1 .
JP13, JP14 B to center Connect outputs from the ADA4899-1 to the inputs of the ADC. The A to center position sets the fully
differential path through the ADA4932-1 .
LK2 Inserted Connects REFIN to the1.2 V external reference.
LK3 Inserted Connects the 4.096 V output from the ADR4540 after buffer AD8031 .
LK6 B Connects the output of the VCM buffer to the VCM of the amplifier.
LK9 A Connects to the 7 V supply coming from the ADP7102 .
LK10 A Connects to the −2.5 V coming from the ADP2300 .
Table 2. On-Board Connectors
Connector Description
J1 SMA low noise, low jitter clock source input.
J2, J10 SMA CNV input. This option is for using the external CNV signal.
J3, J5, J6, J8 SMA analog input. Connects the low noise analog signal source to the inputs of the ADC driver ADA4899-1 , ADA4897-1 , or
ADA4932-1 .
J4 3-pin terminal. This option is for using external bench top supplies. Apply exV
S
, −V
S
, and GND to power amplifiers on
the EVAL-AD7625FMCZ / EVAL-AD7626FMCZ boards.
J9 6-pin (2 × 3) socket. This option is for interfacing with an external ADC driver board.
J7 160-pin FMC 10 mm male VITA 57 connector. This connector mates with the EVAL-SDP-CH1Z board.
J11, J12 SMA low noise, low jitter clock output from the AD9513 .