EV1HMC8362LP6G
/
EV1HMC8364LP6G
User Guide
UG-1787
Rev. 0 | Page 5 of 11
LOOP FILTER
Although the EV1HMC8362LP6G and EV1HMC8364LP6G
boards do not incorporate the entire loop filter, they do provide
the means to filter noise that may appear on the tuning port
when evaluating only the VCOs.
By default, a 100 pF capacitor (C12) is placed near Pin 27
(V
TUNE
) of the
HMC8362
and
HMC8364
to filter high frequency
noise that may couple onto the tune port path when evaluating
the various VCOs.
The EV1HMC8362LP6G and EV1HMC8364LP6G boards also
include placements for the last pole of a loop filter on the tuning
port path for use when configuring the
HMC8362
and
HMC8364
with an Analog Devices, Inc., standalone phase-
locked loop (PLL) product like the
ADF41513
. Although the
tuning port path and input capacitance of the VCO makes up
the last pole of the loop filter, this user guide refers to the last
pole as that which can be accessed by the user.
Due to the increased length of the loop filter path that typically
occurs when using evaluation boards to build a synthesizer,
placement of the loop filter components becomes critical. Loop
stability and overall performance is improved by placing the
first pole of the loop filter as close to the PLL charge pump (CP)
output as possible while placing the last pole as close to the
tuning port pin (V
TUNE
) of the VCO. The placement of any
additional poles that may exist between the first and last pole of
the loop filter are not as critical. Therefore, these filter poles
remain on the
ADF41513
. The placements for this last pole on
the EV1HMC8362LP6G and EV1HMC8364LP6G are
populated by default and consist of R32 (0 Ω by default) and a
100 pF capacitor (C12) near Pin 27 (V
TUNE
). Users can replace
these components with the proper values as needed.
The tuning voltage requirements of the
HMC8362
and
HMC8364
(1.0 V to 13.5 V) require an active loop filter to be
used unless the charge pump of the PLL can output at least 14 V.
The PLL evaluation board typically includes placements for the
operational amplifier, its biasing circuitry, and any component
placements. Therefore, these components are not included on
the EV1HMC8362LP6G and EV1HMC8364LP6G.
SMA Connector J2 provides a means to connect the PLL CP
output to the tuning port (VTUNE) when the
EV1HMC8362LP6G and EV1HMC8364LP6G are used with an
optional PLL evaluation board. J2 can also be used to manually
tune the VCO within its band when evaluating the open-loop
VCO performance.
DEFAULT CONFIGURATION
All components necessary for local oscillator generation are
inserted on the EV1HMC8362LP6G and EV1HMC8364LP6G
boards.
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