ADT7476
Rev. B | Page 27 of 72
STICKY
STATUS BIT
HIGH LIMIT
TEMPERATURE
CLEARED ON READ
(TEMP BELOW LIMIT)
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
SMBALERT
0
53
82
-03
0
Figure 29. SMBALERT and Status Bit Behavior
Figure 29 shows how the SMBALERT output and sticky status
bits behave. Once a limit is exceeded, the corresponding status
bit is set to 1. The status bit remains set until the error condition
subsides and the status register is read. The status bits are refer-
red to as sticky because they remain set until read by software.
This ensures that an out-of-limit event cannot be missed if
software is polling the device periodically.
Note that the SMBALERT output remains low for the entire
dura-tion that a reading is out-of-limit and until the status
register has been read. This has implications for how software
handles the interrupt.
Handling SMBALERT Interrupts
To prevent the system from being tied up servicing interrupts, it
is recommend that the SMBALERT interrupt be handled as
follows:
1.
Detect the SMBALERT assertion.
2.
Enter the interrupt handler.
3.
Read the status registers to identify the interrupt source.
4.
Mask the interrupt source by setting the appropriate mask
bit in the interrupt mask registers (0x74 and 0x75).
5.
Take the appropriate action for a given interrupt source.
6.
Exit the interrupt handler.
7.
Periodically poll the status registers. If the interrupt status
bit has cleared, reset the corresponding interrupt mask bit
to 0. This causes the SMBALERT output and status bits to
behave as shown in Figure 30.
Masking Interrupt Sources
Interrupt Mask Register 1 and Interrupt Mask Register 2 are
located at Register 0x74 and Register 0x75. These allow individ-
ual interrupt sources to be masked out to prevent SMBALERT
interrupts. Note that masking an interrupt source prevents only
the SMBALERT output from being asserted; the appropriate
status bit is set normally.
STICKY
STATUS BIT
HIGH LIMIT
TEMPERATURE
CLEARED ON READ
(TEMP BELOW LIMIT)
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
INTERRUPT
MASK BIT SET
SMBALERT
05
38
2-
0
31
INTERRUPT MASK BIT
CLEARED
(SMBALERT REARMED)
Figure 30. How Masking the Interrupt Source Affects SMBALERT Output
Interrupt Mask Register 1 (0x74)
Bit 7 (OOL) = 1, masks SMBALERT for any alert condition
flagged in InterruptStatus Register 2.
Bit 6 (R2T) = 1, masks SMBALERT for Remote 2 temperature.
Bit 5 (LT) = 1, masks SMBALERT for local temperature.
Bit 4 (R1T) = 1, masks SMBALERT for Remote 1 temperature.
Bit 3 (5 V) = 1
,
masks SMBALERT for 5 V channel.
Bit 2 (V
CC
) = 1, masks SMBALERT for V
CC
channel.
Bit 1 (V
CCP
) = 1, masks SMBALERT for V
CCP
channel.
Bit 0 (2.5 V/THERM) = 1, masks SMBALERT for 2.5 V/THERM.
Interrupt Mask Register 2 (0x75)
Bit 7 (D2) = 1, masks SMBALERT for Diode 2 errors.
Bit 6 (D1) = 1, masks SMBALERT for Diode 1 errors.
Bit 5 (F4P) = 1, masks SMBALERT for Fan 4 failure.
If the TACH4 pin is used as the THERM input, this bit masks
SMBALERT for a THERM event. If the TACH4 pin is used as
GPIO6, setting this bit masks interrupts related to GPIO6.
Bit 4 (FAN3) = 1, masks SMBALERT for Fan 3.
Bit 3 (FAN2) = 1, masks SMBALERT for Fan 2.
Bit 2 (FAN1) = 1, masks SMBALERT for Fan 1.
Bit 1 (OVT) = 1, masks SMBALERT for overtemperature
(exceeding THERM temperature limits).
Bit 0 (12 V/VC) = 1, masks SMBALERT for 12 V channel or for
a VID code change, depending on the function used.
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