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TWI General Operation
11-12
ADSP-BF537 Blackfin Processor Hardware Reference
The clock low field of the
TWI_CLKDIV
register number of internal time ref-
erence periods the serial clock (
SCL
) is held low. It is represented as an
8-bit binary value.
Error Signals and Flags
The following sections describe the TWI error signals and flags.
TWI Master Status
The TWI master mode status register (
TWI_MASTER_STAT
) holds informa-
tion during master mode transfers and at their conclusion. Generally,
master mode status bits are not directly associated with the generation of
interrupts but offer information on the current transfer. Slave mode oper-
ation does not affect master mode status bits.
•
Bus busy
(
BUSBUSY
)
Indicates whether the bus is currently busy or free. This indication
is not limited to only this device but is for all devices. Upon a start
condition, the setting of the register value is delayed due to the
input filtering. Upon a stop condition the clearing of the register
value occurs after t
BUF
.
[1] The bus is busy. Clock or data activity has been detected.
[0] The bus is free. The clock and data bus signals have been inac-
tive for the appropriate bus free time.
•
Serial clock sense
(
SCLSEN
)
This status bit can be used when direct sensing of the serial clock
line is required. The register value is delayed due to the input filter
(nominally 50 ns). Normal master and slave mode operation
should not require this feature.
Содержание Blackfin ADSP-BF537
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Страница 90: ...Development Tools 1 32 ADSP BF537 Blackfin Processor Hardware Reference ...
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Страница 720: ...Electrical Specifications 11 60 ADSP BF537 Blackfin Processor Hardware Reference ...
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Страница 1162: ...G 26 ADSP BF537 Blackfin Processor Hardware Reference ...
Страница 1218: ...Index I 56 ADSP BF537 Blackfin Processor Hardware Reference ...