Analog Devices ADSP-BF592 EZ-KIT Lite, Руководство пользователя

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ADSP-BF592 EZ-KIT Lite Evaluation System Manual 2-3
ADSP-BF592 EZ-KIT Lite Hardware Reference
power-on-self test (POST) example in the ADSP-BF592 installation
directory for information on how to set up the TWI interface.
The core voltage and clock rate can be set up on the fly by the processor.
The input clock is 25 MHz. The core and system clock are programmable
via the
PLL_DIV
register of the processor. The core clock runs at a maxi-
mum of 400 MHz. The default boot mode for the processor is SPI flash
boot. See
“Boot Mode Select Switch (SW4)” on page 2-8 for information
on how to change the default boot mode.
Programmable Flags
The processor has 32 general-purpose input/output (GPIO) signals spread
across two ports (
PF
and
PG
). The pins are multi-functional and depend on
the ADSP-BF592 processor setup. Table 2-1 and Table 2-2 show how the
programmable flag pins are used on the EZ-KIT Lite.
Table 2-1. Port F Programmable Flag Connections
Processor Pin Other Processor Function EZ-KIT Lite Function
PF0 DRSEC1/PPI8/WAKEN1
Default:
LED0
.
Land grid array, expansion interface II
PF1 DRPRI1/PPI9
Default:
LED1
.
Land grid array, expansion interface II
PF2 RSCLK1/PPI10
Default:
LED2
.
Land grid array, expansion interface II
PF3 RFS1/PPI11
Default:
PB0
.
Land grid array, expansion interface II
PF4 DTSEC1/PPI12
Default:
PB1
.
Land grid array, expansion interface II
PF5 DTPRI1/PPI13
Default:
CHARGE_OFF
.
Land grid array, expansion interface II
PF6 TSCLK1/PPI14
Default: Not used.
Land grid array, expansion interface II