ADSP-219x/2192 DSP Hardware Reference B-15
ADSP-2192 DSP Peripheral Registers
2
RDIS
Reset Disable.
When 1, disables a PCI/ISA/CBUS bus reset from affecting
any portions of the ADSP-2192 except the bus interface
itself. When 0 (default), a bus reset causes the DSPs and
AC’97 subsystem to be reset.
Note: If
RDIS
is set, the DSP can detect that the bus is in
reset by the
PCIRST
bit in the
CMSR
register. Un-masked Bus
Reset affects the DSPs, the GPIOs, the AC’97, and the
PCI/USB interface.
Un-masked Bus Reset does not affect the Mailboxes or
EEPROM.
Note that the DSP memory pipeline (last 2 writes per bank) is
lost upon reset. If desired, it may be flushed by three writes
in a row to the same location.
Note: This bit resets to zero.
3
XON
XTAL Force On.
When 1, causes the XTAL oscillator to run even if all other
subsystems are powered down. This permits access to the
on-chip control registers when the part is powered down. If
the chip and the XTAL oscillator are powered off, attempting
to write PDC registers including this one will result in power-
ing up the XTAL and setting the
XON
bit. The write will suc-
ceed, after a delay for the oscillator to stabilize. Subsequent
writes or reads should not be attempted until the oscillator
has stabilized, about 8K clocks or 333us.
When 0, the XTAL oscillator stops whenever it is not needed
by any on-chip subsystem.
Note: This bit resets to zero.
Table B-4. SYSCON Register Bit Descriptions (Continued)
Bit Position
Bit Name
Description
