AN-695
Application Note
Rev. C | Page 8 of 12
EVALUATION BOARD LAYOUT
Figure 10 through Figure 13 show the layout of the ADN8831
evaluation board.
Seven important guidelines are helpful when designing an
ADN8831 evaluation board layout. Refer to Figure 9 for the
part numbers listed here.
1.
The ground terminals of decoupling capacitors from the
PVDD to PGND and the PWM LC output filter capacitors
must be tied together to reduce the power rail ripple. Using
PCB traces or a ground plane (with long current paths) to
connect these two components may generate, rather than
reduce, the power rail ripple (supply pumping).
2.
The two source terminals of the PWM MOSFETs must
be connected directly or through a thick trace (>1 mm)
to the terminals of the power supply decoupling capacitors
(C16 and C19).
3.
ADN8831-EVALZ uses a 4-layer PCB layout. Several
recommendations to consider when using a 4-layer PCB
follow.
Use one internal layer as the ground plane, the other
internal layer for signal traces. Use both top and bottom
layers as heat sinks for the ADN8831 IC, the output
filter inductor, and the output MOSFETs (both on the
linear and on the PWM sides).
Avoid conducting high current on the ground plane.
Always differentially run the PCB traces for critical
signal paths. For example, run a dedicated parallel
trace for the analog ground (AGND) with the
R2 Pin 1 trace; both are for connecting the two
terminals of the thermistor. This ensures that any
interference coupled on the thermistor traces can
cancel each other.
The low frequency temperature control circuit can be
degraded easily by high frequency interference due to
the rectifier effect. This effect refers to the phenomenon
that occurs when a high frequency signal interferes
with a low frequency circuit; the interference signal is
rectified, or coupled, onto dc or lower frequency signals,
thus affecting the operation of the circuit. When high
frequency interference is unavoidable, use a small
capacitor of up to 100 nF connected across the
thermistor and mounted close to the controller to
decouple the high frequency interference.
4.
Ensure that the power supply decoupling capacitors have a
total value of >40 μF. SMT multilayer ceramic capacitors of
type X5R or X7R are the recommended capacitors. These
types of capacitors have stable capacitance over temperature
and very low equivalent series resistance (ESR).
5.
The resistor placed between AVDD and PVDD is 1 Ω to
10 Ω in value.
6.
Design the AGND and PGND carefully and connect both
grounds at where the lowest current density exists on
the PCB.
7.
Because the ADN8831 and the MOSFETs take huge
amounts of current, heat can build up quickly. For stable
component performance, a metal heat sink design can
relieve the component heat dissipation problem, especially
at the PWM MOSFET side. When designing your layout,
it is good practice to leave adequate space between the
components. To ensure that your heat sink design is
adequate, contact Analog Devices for design review
support of your layout before fabricating the PCB.
