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Evaluation Board 
User Guide 

UG-XXX 

 

Rev. A | Page 11 of 14 

DIGITAL RAMP GENERATOR (DRG) 

 

 

Figure 12. Digital Ramp Generator Window

 

 

Digital Ramp Generator is synonymous to linear sweep. The 
ramp generation parameters allow the user to control both the 
rising and falling slopes of the ramp, the upper and lower 
boundaries of the ramp, the step size and step rate of the rising 
portion of the ramp, and the step size and step rate of the falling 
portion of the ramp. This is digitally generated with a 32-bit 
output resolution that can be programmed to represent 
frequency, phase, or amplitude. Refer to AD9915 datasheet for 
more information on DRG. 

There are three general parameters that a DRG requires: region 
for the linear sweep, step size, and step rate. In order to specify 
the region, two values must be chosen (Sweep 0 and Sweep 1 
wherein each contains a different representation, depending on 
the mode; MHz for frequency, degree for phase, and a scalar 
value for amplitude) and it must be within the allowable range. 
Step size indicates the value that would be incremented while 
step rate determines the time interval/period for that increment 
(in µs).  

To use the digital ramp generator (DRG) function of the 
AD9915, select the 

Enable Digital Ramp Generator

 

checkbox. Under 

Mode

 section, select the parameter to be 

generated –frequency, phase, or amplitude. In the 

Settings

 

section, The 

Auto Clear Digital Ramp Accumulator 

checkbox allows you to set the clear digital ramp accumulator 
bit when the I/O update signal is applied or when there is a 
profile change. The clear bit is then released. 

The 

Clear Digital Ramp Accumulator

 checkbox allows you 

to set and keep the digital ramp accumulator cleared until that 
bit is cleared. The 

Load DRR @I/O Update

 checkbox allows 

you to reload the digital ramp rate when an I/O update is issued 
or when there is a profile change.  

Sweep Frequency 0

 and 

Sweep Frequency 1 

are the starting 

and stopping frequencies of the ramp, respectively. Note that 
this is frequency, phase, or amplitude depending on which ramp 
generator is selected. It is important that the value in the Sweep 
0 register is always less than the value in the Sweep 1 register.  

Содержание AD9915

Страница 1: ...sweep capability and programmable modulus for board control and data analysis Factory tested and ready to use PACKAGE CONTENTS AD9915 evaluation board AD9915PCBZ installation software CD USB cable GEN...

Страница 2: ...s Settings 3 Evaluation Board Layout 4 Evaluation Board Software 5 Software Installation 5 Device Driver Installation 5 Starting the Software 5 Running the Software Under Windows 7 6 ICON Description...

Страница 3: ...nto the ADCLK925 could dramatically limit the AD9915 in close phase noise performance Refer to theADCLK925 data sheet for details on the maximum input speeds and input sensitivities JUMPERS SETTINGS U...

Страница 4: ...t This is the input for the external reference clock signal Refer to AD9915 datasheet for reference input range Power Supply Connections Provides all necessary supply voltages needed by the AD9915 and...

Страница 5: ...ps 3 5 STARTING THE SOFTWARE Before you start the software make sure that the AD9915 evaluation board is powered up and connected to the PC and the LED D200 USB status is on Refer to Power Supply Conn...

Страница 6: ...C The main website is indicated below http www microsoft com windows virtual pc They have specific instructions for the installation depending on the version of Windows 7 that your computer has so ref...

Страница 7: ...SCRIPTION OF CONTROL WINDOW The ICON description window is built to allow ease of access to different actions Another way of accessing these icons is by clicking the Actions tab and select among the a...

Страница 8: ...ection allows you to enable the internal PLL of AD9915 PLL enable is used to activate internal PLL of AD9915 The default setting of this box is disabled check box cleared indicating that the internal...

Страница 9: ...the Enable sine output checkbox Matched Latency Enabled allows you to align the application of the frequency tuning word the phase offset word and the amplitude scale factor at the same time If this b...

Страница 10: ...this ICON must be clicked for all initial setups andevery time the REF CLK frequency is changed 7 Click the profile tab to go to the profile windows 8 Enable profile mode via check box and enter the d...

Страница 11: ...ithin the allowable range Step size indicates the value that would be incremented while step rate determines the time interval period for that increment in s To use the digital ramp generator DRG func...

Страница 12: ...mp The Ramp Finished indicator turns on when the ramp is complete PROGRAMMABLE MODULUS WINDOW Figure 13 Programmable Modulus Window The chip is in programmable modulus mode when the Enable Programmabl...

Страница 13: ...stalled at its last state otherwise the DRG operates normally EXTAMPCTL sets the OSK feature on either manual or automatic mode EXTPDCTL is a flag input that would initiate the programmed power down m...

Страница 14: ...uction composed of the Data the Address the Length Bits and the Type of Instruction Read Write The order of the instructions can be seen from the small window which is on the left side of the REGISTER...

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