Evaluation Board User Guide
UG-169
One
Technology
Way
•
P.O.
Box
9106
•
Norwood,
MA
02062-9106,
U.S.A.
•
Tel:
781.329.4700
•
Fax:
781.461.3113
•
www.analog.com
Evaluating the AD9523/AD9524 Clock Generator
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS.
Rev. 0 | Page 1 of 12
FEATURES
Simple power connection using USB connection and
on-board LDO voltage regulators
LDOs are easily bypassed for power measurements
AC-coupled differential SMA connectors
SMA connectors for
2 reference inputs
2 PLL status outputs
1 reference test input
2 VCXO interface inputs/outputs
Microsoft Windows®–based evaluation software
with simple graphical user interface
On-board PLL loop filter
Easy access to digital I/O and diagnostic signals
via I/O header
Status LEDs for diagnostic signals
USB computer interface
Software calculator provides flexibility, allowing programming
of almost any rational input/output frequency ratio
GENERAL DESCRIPTION
This user guide describes the hardware and software of the
and
evaluation boards, and includes detailed
schematics and PCB layout artwork. The AD9523 and AD9524
are designed to operate in the same manner. This user guide
serves both boards but refers to the AD9523.
The AD9523 is defined to support the clock requirements for
long-term evolution (LTE) and multicarrier GSM base station
designs. It relies on an external VCXO to provide the reference
jitter cleanup to achieve the restrictive phase noise requirements
necessary for acceptable data converter SNR performance.
The input receivers, oscillator, and zero delay receiver provide
both single-ended and differential operation. When connected
to a 30.72 MHz to 122.88 MHz reference clock and a VCXO of
either 30.72 MHz to 122.88 MHz, the device generates low
noise outputs from a range of 0.96 MHz to 983.04 MHz.
DIGITAL PICTURE OF EVALUATION BOARD
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Figure 1.
AD9523 Evaluation Board