UG-073
Evaluation Board User Guide
Rev. 0 | Page 6 of
12
Table 5. Output Configuration
Clock
Source
DAC Output
Default
Single-Ended
Buffered
Quadrature
Modulator
R15, R16
On
On
On
R11, R38
On
On
On
S3 = S8 = GND
On
S3 = S8 = GND
On
S3 = S8 = GND
R95, R96,
R155, R156
0 Ω
Off
Off
R57, R50
453 Ω
453 Ω
Off
R13, R14,
R52, R53
Off Off 500
Ω
(AD971x)/
50 Ω (AD911x)
R111, R112
Off
On-Off or
Off-On
Clock input
JP55, JP56,
JP76, JP82
Off Off On
J6 NC NC
Modulator
LO
input
J7 NC NC
Modulator
output
TP16
NC
NC
5 V power
(modulator)
TP21 NC
NC
GND
(modulator)
1
NC = no connect.
2
Board default setup allows single-ended views of IOUTB (S4) and QOUTB (S6).
Common-Mode Output Setting
The common mode of the DAC analog outputs is set by default
to be 0 V (R15 and R16 = 0 Ω). It can be changed to use internal
or external common-mode resistors. The AD911x and AD971x
operate safely only within a certain common-mode voltage
range. Refer to the product data sheet to understand these limits.
Table 6. DAC Common-Mode Configuration
Resistors
Common Mode
= 0 V
With External
Resistors
With Internal
Resistors
R15, R16
On
Off
Off
R22, R154
Off
On
Off
R20, R26
On
Off
Off
R19, R21
Off
On
On
R
C
: Common-
Mode Resistor
0 Ω
R22 for IDAC
R154 for QDAC
IR
CM
for IDAC
QR
CM
for QDAC
In the common-mode configuration proposed, the common-
mode voltage for each DAC can be calculated using the formula
V
CM
=
R
C
×
Full-scale current
Output Loads
The AD911x and AD971x provide output current. These
currents are converted to voltages with loading resistors. By
default, the output loads are provided by on-board resistors.
Alternatively, on-chip resistors can be used. Jumper setting
should be implemented for the option chosen.
Table 7. DAC Output Load Configuration
Resistors
On-Board Load
Resistor Default
On-Chip Load
Resistors
R57, R50
On
Off
JP32, JP33, JP34,
JP35
Off On
R
LOAD
: Load
Resistor
R57 for IDAC
R50 for QDAC
62.5 Ω for AD911x
500 Ω for AD971x
In the load mode configuration proposed, the output voltage for
each DAC can be calculated using the formula:
V
OUTPUT
=
R
LOAD
×
I
OUT
Pin Mode
The AD971x and AD911x evaluation boards have the capability
to function in pin mode. This bypasses the USB SPI control and
allows users who operate with less intricate systems to control
the board in a much simpler fashion. This mode is only useful
when a versatile and full-featured SPI is not needed or is
unavailable.
Change the following hardware settings to operate in pin mode:
1.
Populate JP11 (RESET HIGH). Note that R44, R45, and
R103 remain unpopulated
2.
Pull the TP18, TP19, TP20 test points to high or low states
to control the mode selections.
When the system is set into this control mode, all SPI bits
remain in their default states and certain pins are redefined as
controls. Due to the minimum control provided by this setup,
the internal resistances cannot be set and, therefore, only
external resistor options are available to change the output
current. These are set by the JP7, JP8, JP9, JP16, JP17, and JP20
pin shunt jumpers, as shown in Table 3.
The TP18, TP19, and TP20 test points control the SPI data
input (SDIO), the SPI clock (SCLK), and the SPI chip select
(CSB), respectively. The SDIO control changes the state of
the FORMAT bit (Register 0x02, Bit[7] to either binary (LO)
or twos complement (HI). The SCLK control overrides the
CLKMODE bits (Register 0x14, Bits[1:0]) to be either the
clock in Delay2 of 180
°
(LO) or the clock in Delay1 of 90
°
(HI). The CSB control alters the power-down (PWRDN) bit
(Register 0x01, Bit [5]) to be either powered-up (LO) or
powered-down (HI). All other controls are not implemented
or altered from the default settings, as listed in the SPI Register
Descriptions section of the product data sheets.
