UG-559
Evaluation Board User Guide
Rev. B | Page 4 of 8
EVALUATION BOARD HARDWARE
POWER SUPPLIES
The
AD8338
evaluation board includes the
ADP1720
low
dropout regulator (LDO). The LDO supplies a very clean 5.0 V
supply to the
AD8338
and
ADA4940-1
.
Note that, because the supply input to the evaluation board is
not reverse bias protected, it is important to exercise care when
connecting your power supplies to prevent damage.
INPUT CONTROLS
The
AD8338-EVALZ
has two primary input controls, GAIN
ADJUST and AGC SET (see Figure 1). An external voltage
applied to the respective test points overrides the potentiometer,
allowing for direct electronic control.
The MODE signal can also be overridden with an external
signal by driving the associated test point.
MODES AND INPUT AND OUTPUT SIGNALS
AGC Mode
AGC mode attempts to regulate the output magnitude to a
target rms voltage. This mode requires altering some jumper
settings. As shown in Figure 6, Jumper J10 is shifted by one pin.
For easy identification, refer to the silkscreen reference on the
evaluation board. (See Figure 7 for electrical information;
changing connection from Pin 2 and Pin 3 to Pin 1 and Pin 2.)
This connects the GAIN pin to the DETO pin, and puts the
evaluation board into AGC mode. After altering the jumper
settings, set the rms voltage by applying a voltage of the 0 V to
3.0 V range on the VAGC pin.
When the AGC mode is disabled, the MODE pin selects the
direction of the gain slope, either positive or negative. While the
AGC mode is disabled, the GAIN pin directly controls the gain
with an input ranging between 0.1 V and 1.1 V. When the AGC
circuit is not in use, tie the VAGC pin to VREF.
In this mode, the user controls the rms output level through
applying an input signal to VAGC. For the lowest gain, VAGC is
tied to VREF, where the loop attempts to attenuate the output to
0 V rms.
As the input to VAGC moves away from the 1.5 V of VREF (in
either the positive or negative direction), the gain increases.
Enable or disable offset nulling through the removal or placement
of Jumper J12. By default, the jumper is not installed, enabling
offset nulling. The application of the offset nulling feature applies a
capacitor between OFNS and VREF, where the internal correction
circuit passes signals of a higher frequency.
Input Signals
The signal inputs to the evaluation board start with SMA con-
nectors designated by J3 and J4. On the board, these signals are
terminated to ground with 49.9 Ω resistors. The inputs are then
fed into the inputs of the
AD8338
directly (in the default config-
uration), or to the inputs of an
ADA4940-1
differential amplifier.
In the worst-case scenario, the effective input impedance seen
by the signal generator is 45 Ω (a VSWR match of 1.1:1).
Output Signals
The
AD8338
outputs swing nearly up to 1.5 V relative to VREF,
regardless of device power supply. On the evaluation board,
these outputs are ac-coupled through 0.1 μF capacitors and
should not be loaded with terminating values less than
500 Ω (per each output). Below 500 Ω, the linearity of the
outputs begins to degrade.
DEFAULT OPERATION AND JUMPER SELECTION
SETTINGS
Factory Default Configuration
The
AD8338
evaluation board ships with a default configuration
shown in Figure 4 whereby offset nulling is enabled, MODE is
set to high, and the system gain increases by rotating GAIN
ADJ clockwise.
Figure 4. Standard Jumper Configuration
1
1510-
007
J5
J6
J7
J8
J11
J9
J12
J10
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