UG-386
AD9642/AD9634/AD6672 User Guide
LAYOUT: ROUTE ALL TRACES TO THE
TYCO CONN ON TOP OF BOARD
SPI & FPGA CONN.
USING FIFO5
(UNUSED PINS REMOVED)
NOTE: THIS SYMBOL IS DRAWN GIVEN INPUT 1 LOGIC
LAYOUT: PLACE C602 NEAR DUT
C604
C601
C603
C602
R645
R644
R643
R646
R637
R636
R635
R633
R629
1
TP_DUT_SDIO
1
TP_CYP_SDIO
1
TP612
1
TP611
1
TP610
1
TP_DUT_SCLK
1
TP_DUT_CSB
1
TP609
1
TP608
1
TP607
1
TP606
1
TP605
R628
R627
B9
B8
B7
B6
B5
B4
B3
B2
B10
B1
P602
A9
A8
A7
A6
A5
A4
A3
A2
A10
A1
P602
C9
C8
C7
C6
C5
C4
C3
C2
C10
C1
P602
D9
D8
D7
D6
D5
D4
D3
D2
D10
D1
P602
BG9
BG8
BG7
BG6
BG5
BG4
BG3
BG2
BG10
BG1
P602
DG9
DG8
DG7
DG6
DG5
DG4
DG3
DG2
DG10
DG1
P602
R606
R616
R608
B9
B8
B7
B6
B5
B4
B3
B2
B10
B1
P601
A9
A8
A7
A6
A5
A4
A3
A2
A10
A1
P601
D9
D8
D7
D6
D5
D4
D3
D2
D10
D1
P601
C9
C8
C7
C6
C5
C4
C3
C2
C10
C1
P601
DG9
DG8
DG7
DG6
DG5
DG4
DG3
DG2
DG10
DG1
P601
BG9
BG8
BG7
BG6
BG5
BG4
BG3
BG2
BG10
BG1
P601
R613
R609
R605
R603
R626
4
6
5
2
3
1
U602
4
2
1
3
U603
7
9
10
8
U603
14
12
11
13
U603
R615
17
19
20
18
U603
5
16
15
6
U603
R602
R612
R611
R601
R610
4
6
5
2
3
1
U601
D2/D3+
DNI
D6/D7-
D10/D11-
D4/D5+
D10/D11-
100
D12/D13+
D12/D13-
D12/D13-
D12/D13+
D8/D9+
D10/D11+
D6/D7+
D10/D11+
D0/D1-
D4/D5-
D8/D9-
D8/D9-
D8/D9+
D4/D5+
D0/D1+
D6/D7+
D6/D7-
D4/D5-
100
100
DNI
100
DCO-
D2/D3-
D2/D3+
D2/D3-
100
DNI
DCO+
100
D0/D1-
D0/D1+
DNI
10K
3P3V_DIGITAL
1.1K
CYP_SDIO
KP_VDDIO
DNI
3P3V_DIGITAL
0.1UF
DNI
0
0
ADG734BRUZ
DCO+
DNI
DNI
DNI
CYP_SDO
DNI
0
DNI
DNI
DNI
CYP_SCLK
10K
1.1K
CYP_CSB
100K
DNI
DNI
DRVDD
10K
1.1K
DNI
USB_CSB2
10K
DUT_SDIO
CYP_SDI
6469169-1
0
0
NC7WZ16P6X
CYP_CSB
CYP_CSB2
DNI
FPGA_SCLK
DUT_CSB
DNI
ADG734BRUZ
DNI
DNI
ADG734BRUZ
10K
FAST_SPI_EN
DNI
DUT_SCLK
ADG734BRUZ
DNI
FAST_SPI_EN
ADG734BRUZ
3P3V_DIGITAL
DRVDD
DRVDD
0.1UF
DRVDD
NC7WZ07P6X
FPGA_CSB
100K
DCO-
DNI
DNI
100
100
DNI
DNI
DNI
0.1UF
DNI
0.1UF
100K
CYP_CSB2
3P3V_DIGITAL
DNI
10K
FAST_SPI_EN
CYP_SDO
CYP_SDI
CYP_SCLK
FPGA_SCLK
FPGA_CSB
FPGA_SDIO
FPGA_SDIO
Y2
Y1
A2
A1
GND
VCC
SB
D
IN
SB
D
IN
SB
D
IN
SB
D
IN
VSS
GND
NC15
VDD
PLUG HEADER
PLUG HEADER
PLUG HEADER
PLUG HEADER
PLUG HEADER
PLUG HEADER
PLUG HEADER
PLUG HEADER
PLUG HEADER
PLUG HEADER
PLUG HEADER
PLUG HEADER
VCC
Y1
A1
A2
GND
Y2
10593-
024
Figure 23. SPI Configuration Circuit and FIFO Board Connector Circuit
Rev. A | Page 18 of 26