AD9642/AD9634/AD6672 User Guide
UG-386
PECL/CML/LVDS CLK CIRCUITRY
ACTIVE CLOCK PATH
5
4
3
1
T501
C510
C509
C521
C520
C516
C515
C514
C548
C546
C545
C543
C544
C542
C541
C540
C547
C539
C538
C536
C537
C535
C519
C518
C517
C505
C506
C507
C504
C502
C501
C513
C512
C531
L507
C530
5
4
3
2
1
J503
R521
R520
R546
R519
R545
R544
R536
R535
R532
R531
R527
R526
R525
R524
71
70
42
48
54
63
30
36
69
18
13
2
39
45
51
60
27
33
66
17
55
56
23
22
21
19
6
5
4
3
24
16
72
15
PAD
37
38
40
41
43
44
46
47
49
50
52
53
58
59
61
62
64
25
26
28
29
31
32
34
35
65
67
68
10
9
8
11
7
14
12
1
57
20
U501
2
1
E502
L506
1
TP505
1
TP504
2
1
E501
C527
C534
C526
C525
C524
L501
L502
L503
L504
L505
R501
R510
R511
R512
R518
R517
R515
R516
1
TP501
R509
C508
C511
R507
R508
CR501
CR502
R505
R503
R604
R502
C503
R506
R513
R514
4
6
5
2
3
1
U300
6
1
5
4
3
Y501
1
TP502
1
TP503
5
4
3
2
1
J502
0.1UF
DNI
MABA-007159-000000
0.1UF
100
49.9
DNI
49.9
0.1UF
45OHMS
45OHMS
DNI
100
0.1UF
STATUS1/SP1
DNI
3.3V_OUT_4-13
CYP_SDO
USB_CSB2
3.3V_REF
3.3V_OUT_4-13
0.001UF
0.001UF
DNI
0.1UF
0.1UF
0.1UF
0.1UF
SI04
0.1UF
3.3V_OUT_0-3
1.8V_OUT_0-13
200
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
1.8V_OUT_0-13
0.1UF
1.8V_OUT_0-13
0.1UF
0.1UF
3.3V_OUT_4-13
0.1UF
0.1UF
1.8V_OUT_0-13
3.3V_OUT_0-3
0.1UF
100
49.9
CLK_IN-
0.1UF
49.9
0.1UF
0.1UF
60-800MHZ
0.1UF
3.3V_PLL1
0.33UF
0.47UF
100
OUT0
OUT0_N
OUT2_N
3.3V_OUT_4-13
1.8V_OUT_0-13
OUT13
OUT13_N
CYP_SDI
SYNCB
PDB
3.3V_PLL2
3.3V_PLL1
DNI
OUT2
10UF
3.3V_PLL1
10UF
3.3V_OUT_0-3
3.3V_OUT_4-13
3.3V_OUT_4-13
DNI
3.3V_OUT_0-3
100
100
100
STATUS0/SP0
100
100
3P3V_ANALOG
1K
10K
10K
1UH
49.9
100
100
10K
10K
200
LNJ314G8TRA (GREEN)
1UH
1UH
1UH
100
1UH
10K
100
VCXO_CTRL
0
DNI
0
TBD0402
3.3V_REF
100
10K
RESETB
3.3V_REF
49.9
LNJ314G8TRA (GREEN)
3P3V_DIGITAL
0.47UF
0.47UF
3.3V_REF
10UF
10UF
10UF
10UF
1UH
3.3V_PLL2
NC7WZ16P6X
3.3V_OUT_4-13
12PF
0.33UF
CYP_SCLK
3.9NH
CLK_OUT-
EEPROM_SEL
1P8V_CLOCK
AD9523
0.1UF
SEC
PRI
VDD_1_8_OUT6_7
VDD_1_8_OUT4_5
VDD_1_8_OUT2_3
VDD_1_8_OUT0_1
SCLK_SCL
PAD
PLL1_OUT
ZD_IN_N
ZD_IN
OUT0
OUT0_N
VDD3_OUT0_1
OUT1
OUT1_N
OUT2
OUT2_N
VDD3_OUT2_3
OUT3
OUT3_N
EEPROM_SEL
STATUS0_SP0
STATUS1_SP1
OUT4
OUT4_N
VDD3_OUT4_5
OUT5
OUT5_N
OUT6
OUT6_N
VDD3_OUT6_7
OUT7
OUT7_N
VDD_1_8_OUT8_9
OUT8
OUT8_N
VDD3_OUT8_9
OUT9
OUT9_N
VDD_1_8_OUT10_11
OUT10
OUT10_N
VDD3_OUT10_11
OUT11
OUT11_N
VDD_1_8_OUT12_13
OUT12
OUT12_N
VDD3_OUT12_13
OUT13
OUT13_N
REF_TEST
SDO
SDIO_SDA
CS_N
RESET_N
VDD3_REF
SYNC_N
REF_SEL
PD_N
LDO_VCO
VDD3_PLL2
LDO_PLL2
LF2_EXT_CAP
OSC_IN_N
OSC_IN
OSC_CTRL
LF1_EXT_CAP
REFB_N
REFB
REFA_N
REFA
VDD3_PLL1
LDO_PLL1
Y2
Y1
A2
A1
GND
VCC
OUT-
OUT+
VC
VCC
GND
LAYOUT: SMA'S SHOULD BE 540 MILS CENTER TO CENTER
LAYOUT: SHARE PADS WITH ACTIVE CLOCK PATH R'S
PASSIVE CLOCK
CLK
R543
5
4
3
1
T503
R528
C533
C532
C523
C529
C522
R523
R522
R542
R541
R533
R534
R539
1
2
3
CR503
R540
R537
R529
5
4
3
2
1
J505
6
4
2
3
1
T502
R538
R530
5
4
3
2
1
J506
CLK-
CLK+
DNI
100
MABA-007159-000000
33
0
0
33
DNI
0
0
390PF
DNI
390PF
DNI
390PF
49.9
DNI
DNI
49.9
0
DNI
390PF
ADT1-1WT+
0.1UF
DNI
0
0
CLK_IN-
0
DNI
DNI
0
DNI
CLK_OUT-
DNI
SEC
PRI
10593-023
Figure 22. Default and Optional Clock Input Circuits
Rev. A | Page 17 of 26
