AMI 420, Инструкции по установке, эксплуатации и обслуживанию, Страница: 99 / 134

Rev. 7
81
Remote Interface Reference
Status System Commands
‡
*SRE?
The
*SRE?
query returns a decimal sum which corresponds to the binary-
weighted sum of the bits enabled by the last
*SRE
command.
‡
*CLS
Clears the Standard Event register and the error buffer.
‡
*ESR?
Returns the contents of the Standard Event register as a binary-weighted
sum.
‡
*ESE <
enable_value
>
Enables bits in the Standard Event register to be reported in the
“Standard Event” bit (bit 5) of the Status Byte register. To enable bits, you
must write a decimal
<
enable_value
>
which corresponds to the binary-
weighted sum of the bits you wish to enable. Refer to Table 4-2 on page 74
for more information. For example, to enable all categories of error
messages to be reported in bit 5 of the Status Byte register, send:
*ESE 60;
‡
*ESE?
The
*ESE?
query returns a decimal sum which corresponds to the binary-
weighted sum of the bits enabled by the last
*ESE
command.
‡
*PSC {0|1}
Power-On Status Clear. If
*PSC 1
is in effect, the Standard Event enable
register and the Status Byte enable register are cleared at power on. If
*PSC 0
is in effect, the enable registers are not cleared at power on. The
default setting is “1”.
‡
*PSC?
Returns the Power-On Status Clear setting currently in effect. A value of
“0” indicates the enable registers are not cleared at power on; a value of “1”
indicates the enable registers are cleared at power on.
‡
*OPC
Sets the “Operation Complete” bit (bit 0) of the Standard Event register
when executed. See page 74 for a complete discussion.
‡
*OPC?
Returns “1” to the requesting interface when executed. See page 75 for
more information.