AMD Elan SC520, Руководство пользователя

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Clock Generation and Control
Élan™SC520 Microcontroller User’s Manual 5-7
5.5 OPERATION
The clocks on the ÉlanSC520 microcontroller are generated from two local oscillators.
The 32.768-kHz oscillator is used to drive PLL1 (1.47456-MHz PLL), which in turn drives
PLL2 (36.864-MHz PLL). The 36.864-MHz clock is divided by 2 to produce the 18.432-
MHz UART clock. It is divided by 31 to produce the 1.1882-MHz PIT clock.
The 33-MHz oscillator produces the 33-MHz PCI and CPU clocks. The 33-MHz oscillator
is also used to drive PLL3 (66-MHz PLL) to produce the SDRAM clock.
5.5.1 Internal Clocks
5.5.1.1 CPU
The Am5
x
86 CPU bus frequency in the ÉlanSC520 microcontroller is always 33 MHz;
however, the Am5
x
86 CPU core frequency is programmable to be 100 MHz or 133 MHz.
The clock speed of the Am5
x
86 CPU core defaults to 100 MHz, but can be changed
dynamically via the Am5
x
86 CPU Control (CPUCTL) register (MMCR offset 02h). Clocking
considerations for the Am5
x
86 CPU are described in “Clocking Considerations” on
page 7-4.
The ÉlanSC520 microcontroller supports either a 33.000-MHz or 33.333-MHz crystal as
the 33-MHz clock source.
5.5.1.2 PCI Bus
The PCI bus system clock on the ÉlanSC520 microcontroller runs at 33 MHz. The PCI bus
system clock (CLK) is described in “PCI Clocking” on page 9-5, as is usage of the two PCI
bus clock pins, CLKPCIIN and CLKPCIOUT.
The CLKPCIOUT pin is a 33-MHz clock output for the PCI bus devices. This signal is derived
from the 33MXTAL2–33MXTAL1 interface.
Note that the ÉlanSC520 microcontroller supports either a 33.000-MHz or 33.333-MHz
crystal. “Running the Élan™SC520 Microcontroller at 33.333 MHz” on page 5-5 details
some important considerations in choosing a crystal for a PCI system.
5.5.1.3 SDRAM Controller
The SDRAM clock runs at 66 MHz, twice the frequency of the 33-MHz oscillator. The refresh
rate of the SDRAM controller is derived from the 32.768-kHz clock. The flexible refresh rate
supports a wide variety of devices.
Clocking considerations for the SDRAM controller, including the CLKMEMIN and
CLKMEMOUT pins, are described in “SDRAM Clocking” on page 10-6.
5.5.1.4 ROM/Flash Interface
The ROM/Flash controller is clocked from the internal Am5
x
86 CPU bus and operates at
33 MHz.
5.5.1.5 GP Bus
The GP-bus interfaces internally to the Am5
x
86 CPU and operates at 33 MHz.