AMD Elan SC520, Руководство пользователя

Страница: 184 / 444

SDRAM Controller
10-6 Élan™SC520 Microcontroller User’s Manual
– For example, banks 0 and 1 can share the SRASA and SCASA signal.
– Likewise, banks 2 and 3 can share the SRASB and the SCASB signal.
■
Two SWE signals are also provided to alleviate single pin loading.
– For example, banks 0 and 1 can share the SWEA signal, and banks 2 and 3 can share
the SWEB signal.
The four SDQM lines, SDQM3–SDQM0, provide byte masking.
■
Each of the four SDQM3–SDQM0 signals is associated with one byte of four throughout
the array. Each SDQMx signal provides an input mask signal for write accesses and an
output enable signal for read accesses.
See Figure 10-3 on page 10-4, which illustrates the connection of SDRAM signals from the
ÉlanSC520 microcontroller to the external SDRAM banks. Since the SDRAM controller
shares the MD31–MD0 data bus with the ROM/Flash controller, the SDRAM controller
guarantees the SDQM3–SDQM0 signals are forced inactive to make sure the SDRAM
devices do not contend with the ROM or Flash devices that may share the data bus.
10.3.2 SDRAM Clocking
The SDRAM device’s clock is sourced from the SDRAM controller interface of the
ÉlanSC520 microcontroller. As shown in Figure 10-1 on page 10-2, there are two clock
pins dedicated for the SDRAM interface.
■
CLKMEMOUT is a 66-MHz clock.
■ CLKMEMIN must be a direct feedback version of CLKMEMOUT.
The SDRAM controller’s data buffers use CLKMEMIN to latch read data coming from the
SDRAM devices. CLKMEMIN is used to compensate for delays associated with board
loading and external buffering (to allow for read data flight time from the SDRAM device).
The allowable delay between CLKMEMOUT and CLKMEMIN is –0.5 to +6.0 ns.
The following describes a typical scenario for SDRAM systems used with the ÉlanSC520
microcontroller. These are general guidelines to demonstrate system considerations and
are not intended for use as system implementations.
The CLKMEMOUT pin has a 24-mA driver and is capable of driving a 50-pF load directly,
without requiring an external clock driver/buffer and still remain under the maximum
allowable delay of 6 ns. A CLKMEMOUT load above 50 pF may result in delays greater
than 6 ns that could jeopardize data integrity. The 50-pF load includes all loads presented
to the CLKMEMOUT pin such as board routing (between CLKMEMOUT and CLKMEMIN),
DIMM connector load, and SDRAM device load.
Table 10-1 shows estimated bank loads as they pertain to SDRAM device data widths. As
shown in Table 10-1, a bank composed of 4-bit devices presents a greater load to the
CLKMEMOUT pin than a bank composed of 8-bit devices. This table does not include board
or connector loads.
Table 10-1 SDRAM Clock Loading Estimates Based on Device Width
Device Width
4-Bit 8-Bit 16-Bit 32-Bit
Device count (per bank) 8 4 2 1
Total SDRAM clock loading (pF) 32 16 8 4