Altera Stratix GX, Руководство пользователя

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9–42 Altera Corporation
Stratix GX Transceiver User Guide January 2005
Recommended Resets
rxanalogreset_inclk <= 1'b1;
pll_areset <= 1'b1;
waitstate_timer <=
WAITSTATE_TIMER_VALUE;
state<= STROBE_TXPLL_LOCKED;
end
else
begin
rxdigitalreset_inclk <= 1'b0;
rxanalogreset_inclk <= 1'b0;
pll_areset <= 1'b0;
state <= IDLE;
end
STROBE_TXPLL_LOCKED: if (sync_reset) //Synchronous Reset
can be asserted in IDLE state (After reset seq has finished)
begin
rxdigitalreset_inclk <= 1'b1;
rxanalogreset_inclk <= 1'b1;
pll_areset <= 1'b1;
state <=
STROBE_TXPLL_LOCKED;
end
//Wait untill the TXPLL is locked to inclk and TX PLL has a
stable output clock which is also fed to RX CRU
else if (pll_locked)
begin
state <= STABLE_TX_PLL;
rxdigitalreset_inclk<= 1'b1;
rxanalogreset_inclk <= 1'b0;
pll_areset <= 1'b0;
end
else
begin
state <= STROBE_TXPLL_LOCKED;
rxdigitalreset_inclk <= 1'b1;
rxanalogreset_inclk <= 1'b1;
pll_areset <= 1'b0;
end
STABLE_TX_PLL: if (sync_reset) //Synchronous Reset can
be asserted in IDLE state (After reset seq has finished)
begin
rxdigitalreset_inclk <= 1'b1;
rxanalogreset_inclk <= 1'b1;
pll_areset <= 1'b1;
state <= STROBE_TXPLL_LOCKED;
end
else if (rx_freqlocked)
begin
state <= WAIT_STATE;