Altera Stratix GX, Руководство пользователя

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Altera Corporation 9–11
January 2005 Stratix GX Transceiver User Guide
Reset Control & Power Down
pll_areset <= 1'b0;
end
else
begin
waitstate_timer <=
waitstate_timer - 1'b1;
rxdigitalreset_inclk<= 1'b1;
rxanalogreset_inclk <=
1'b0;
txdigitalreset<= 1'b0;
pll_areset <= 1'b0;
state <= WAIT_STATE;
end
end
else
begin
rxdigitalreset_inclk<= 1'b1;
rxanalogreset_inclk <= 1'b0;
txdigitalreset<= 1'b0;
pll_areset <= 1'b0;
waitstate_timer <=
WAITSTATE_TIMER_VALUE;
state <= STABLE_TX_PLL;
end
default: state = IDLE;
endcase
end
/*synchronizing the rxdigitalreset to recovered clock domain
If rxdigitalreset is only used for Receive GXB, then
synchronization is needed because
internally the rxdigitalreset is only synchronized to recovered
clock (rx_clkout). In the above description
of the module, a typical user likes to operate on the system clock
or PLD clock domain.
To reset the rx_coreclk domain logic in PLD fabric following reset
is useful
*/
/* rxanalogreset is optional because it is a power down signal.
The longer the duration of assertion of power down
signal, the circuit will go into a true power down state
*/
always @(posedge rx_coreclk or posedge async_reset)
if(async_reset)
begin
rxdigitalreset_rx_coreclk_Q <= 1'b1;
rxdigitalreset <= 1'b1;
end
else
begin
if(receive_digitalreset)
begin
rxdigitalreset_rx_coreclk_Q <= 1'b1;
rxdigitalreset <= 1'b1;
end