Altera Corporation
1–1
May 2007
1. Overview
Features
Overview
The Nios Development Board, Stratix II Edition, provides a hardware
platform for developing embedded systems based on Altera
®
Stratix II
devices. The Nios Development Board, Stratix II Edition provides the
following features:
■
A Stratix II FPGA with more than 13,500 adaptive logic modules
(ALM) and 1.3 million bits of on-chip memory
■
16 MBytes of flash memory
■
2 MBytes of synchronous SRAM
■
32 MBytes of double data rate (DDR) SDRAM
■
On-board logic for configuring the FPGA from flash memory
■
On-board Ethernet MAC/PHY device and RJ45 connector
■
Two 5V-tolerant expansion/prototype headers each with access to 41
FPGA user I/O pins
■
CompactFlash connector for Type I CompactFlash cards
■
32-bit PMC Connector capable of 33 MHz and 66 MHz operation
■
Mictor connector for hardware and software debug
■
RS-232 DB9 serial port
■
Four push-button switches connected to FPGA user I/O pins
■
Eight LEDs connected to FPGA user I/O pins
■
Dual 7-segment LED display
■
JTAG connectors to Altera devices via Altera download cables
■
50 MHz oscillator and zero-skew clock distribution circuitry
■
Power-on reset circuitry
General
Description
The Nios development board comes pre-programmed with a Nios II
processor reference design. Hardware designers can use the reference
design as an example of how to build systems using the Nios II processor
and to gain familiarity with the features included. Software designers can
use the pre-programmed Nios II processor design on the board to begin
prototyping software immediately.
This document describes the hardware features of the Nios development
board, including detailed pin-out information, to enable designers to
create custom FPGA designs that interface with all components on the
board. A complete set of schematics, a physical layout database, and
GERBER files for the development board are installed with the Nios II
development tools in the
<
Nios II EDS install path
>/documents
directory.