Altera Corporation
Reference Manual
2–3
May 2007
Nios Development Board Stratix II Edition
Board Components
The sections that follow describe each component in detail.
Stratix II EP2S60
Device (U60)
U60 is a Stratix II FPGA in a 672-pin FineLine BGA
®
package. The part
number is EP2S60F672C3N.
Table 2–2
lists the device features.
SW9
Factory Config button
Push-button switch to reconfigure the FPGA with the
factory-programmed reference design.
SW10
Reset, Config
Push-button switch to reset the board.
LED0 – LED3, LED6
Configuration status LEDs
LEDs that display the current configuration status of
the FPGA.
Clock Circuitry
Y2
Oscillator
50 MHz clock signal driven to FPGA.
J4
External clock input
Connector to FPGA clock pin.
Power Supply
J26
DC power jack
16 V DC unregulated power source.
D34
Bridge rectifier
Power rectifier allows for center-negative or center-
positive power supplies.
J28, J29, J30, J33 (and
more)
Optional Power Supply
External power supply can be connected for high-
current applications.
Table 2–1. Nios Development Board, Stratix II Edition Components & Interfaces (Continued)
Board Designation
Name
Description
Table 2–2. Stratix II EP2S60 Device Features
LEs 60,440
M4K Memory Blocks
255
Total RAM Bits
2,544,192
Embedded 18x18 Multiplier Blocks
144
Enhanced PLLs
4
Fast PLLs
8
User I/O Pins
718