Altera Nios II, Руководство по разработке аппаратного обеспечения

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Chapter 1: Nios II Hardware Development 1–11
Creating the Design Example
May 2011 Altera Corporation Nios II Hardware Development Tutorial
Figure 1–4 shows the Qsys GUI in its initial state.
Define the System in Qsys
You use Qsys to define the hardware characteristics of the Nios II system, such as
which Nios II core to use, and what components to include in the system. Qsys does
not define software behavior, such as where in memory to store instructions or where
to send the
stderr
character stream.
In this section, you perform the following steps:
1. Specify target FPGA and clock settings.
2. Add the Nios II core, on-chip memory, and other components.
3. Specify base addresses and interrupt request (IRQ) priorities.
4. Generate the Qsys system.
The Qsys design process does not need to be linear. The design steps in this tutorial
are presented in the most straightforward order for a new user to understand.
However, you can perform Qsys design steps in a different order.
Specify Target FPGA and Clock Settings
The Clock Settings and the Project Settings tabs specify the Qsys system's
relationship to other devices in the system.
Figure 1–4. Qsys GUI