Altera CLR-HSMC, Руководство пользователя

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Chapter 5
4B
Demonstrations
This chapter describes the provided reference designs implemented on CLR in combination with
other mother board. These may be the starter point for users to implement application specific codes
and give users a comprehensive understanding of how to control CameraLink Standardized
peripherals.
We choose the STC-CLC1500 as an example and used in the following demonstrations. User can
find its manual in the Datasheet folder on CLR-HSMC system CD. The important specifications are
listed below.

Industry standard camera link interface

10-bit digital camera link base configuration

Resolution of 1360*1024 pixels

Double speed: 28.636 MHz & Normal speed: 14.318 MHz

Progressive Scan
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The example demonstrates a combinational application of digital Camera Link camera and Camera
Link Interface Card on DE4 board.
In this demo, we set the camera to work under Double Speed Operation Mode (DIP Switch setting)
with internal sync and the others at factory default settings. And the CLR is configured to base
mode.
The camera outputs Camera Link Interface specification data to DE4 via the CLR Card.
According to
X
Figure 5-1
X
, the CCD_Capture module captures one frame video streams with sync
signals, then the RAW2RGB module converts them to RGB format. After that, the frame buffer
caches the frame data and sends them to be displayed on a monitor through DVI interface. The
output resolution is 1024*768 with a 65MHz pixel clock.
The complete reference design is also located in the CD-ROM attached. Please refer to the
following diagram to help you read the code provided.