Altera CLR-HSMC, Руководство пользователя

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18
Chapter 4
3B
Components
This chapter gives a simple description of the on board components, such as operational mode,
signaling standard. For more detailed information you could refer to its datasheet which is available
on manufacturer’s website or from our provided system CD.
4
4
.
.
1
1
L
L
V
V
D
D
S
S
2
2
8
8
-
-
B
B
i
i
t
t
C
C
h
h
a
a
n
n
n
n
e
e
l
l
L
L
i
i
n
n
k
k
Two National Semiconductor LVDS 28-bit channel link chip (DS90CR288A) is installed on the CLR board for
receiving LVDS signals from two Camera Link Receiver ports. It converts the LVDS signaling standard into
parallel LVCMOS signals, which then connect to the HSMC connector. It can support a shift clock frequency
from 20 to 85MHz. Some of the key features are listed below:

20 to 85 MHz shift clock support

Up to 2.38 Gbps throughput

Four LVDS channels
4 4 . . 2 2 3 3 V V L L V V D D S S Q Q u u a a d d C C M M O O S S D D i i f f f f e e r r e e n n t t i i a a l l L L i i n n e e D D r r i i v v e e r r
The CLR board features two National Semiconductor DS90LV047A 3V LVDS quad CMOS differential line
driver chip for LVCMOS signals to LVDS signals adapting. It is used to transport the control signals to the
CameraLink ports. Some of the key features are listed below:

Four LVDS channels with enable control

Above 400MHz switch rates

3.3V LVCMOS single-ended signaling and +/- 350mV differential signaling
4 4 . . 3 3 O O p p e e r r a a t t i i o o n n M M o o d d e e
With two receiver ports, the CLR supports Base, Dual Base and Medium CameraLink modes.
Which mode is in use depends on the connected digital camera. Port J2 is designed to host the base
mode CameraLink signals as well as the camera control and serial communication signals. That’s,
five twisted pairs of LVDS wires carries the Base mode CameraLink signals. Two twisted pairs of
LVDS are used for serial communication with the camera and four additional twisted pairs are used