Control
Description
Status
Displays the following status information during a loopback test:
PLL lock—Shows the PLL locked or unlocked state.
Pattern sync—Shows the pattern synced or not synced state. The pattern is
considered synced when the start of the data sequence is detected.
Details—Shows the PLL lock and pattern sync status:
Port
Allows you to specify which interface to test. The following port tests are
available:
QSFP x4
SFP x1
SMA x1
SDI x1
PMA Setting
Allows you to make changes to the PMA parameters that affect the active
transceiver interface. The following settings are available for analysis:
Serial Loopback—Routes signals between the transmitter and the receiver.
VOD—Specifies the voltage output differential of the transmitter buffer.
Pre-emphasis tap
• 1st pre—Specifies the amount of pre-emphasis on the pre-tap of the
transmitter buffer.
• 2nd pre—Specifies the amount of pre-emphasis on the second pre-tap of
the transmitter buffer.
• 1st post—Specifies the amount of pre-emphasis on the first post tap of the
transmitter buffer.
• 2nd post—Specifies the amount of pre-emphasis on the second post tap of
the transmitter buffer.
Equalizer—Specifies the setting for the receiver equalizer.
DC gain—Specifies the DC portion of the receiver equalizer.
4-12
The XCVR Tab
UG-01170
2015.06.26
Altera Corporation
Board Test System
