Figure 3-2: Default Switch Settings on the Bottom
SW5
ON
1
2
3
4
MSEL0
MSEL1
MSEL2
VIDEN
SW4
CLK_SEL
CLK_EN
Si516_FS
FACTORY
RZQ_B2K
ON
1
1
0
1
0
2
3
4
ARRIA 10
MAX V
FMCA
FMCB
SW6
ON
1
2
3
4
5
1. Set DIP switch bank (SW3) to match the following table.
Table 3-1: SW3 DIP PCIe Switch Default Settings (Board Top)
Switch
Board Label
Function
Default Position
1
x1
ON for PCIe x1
ON
2
x4
ON for PCIe x4
ON
3
x8
ON for PCIe x8
ON
4
—
OFF for 1.35 V MEM_VDD power rail
OFF
2. If all of the jumper blocks are open, the FMCA and FMCB VCCIO value is 1.2 V. To change that value,
add shunts as shown in the following table.
Table 3-2: Default Jumper Settings for the FPGA Mezzanine Card (FMC) Ports (Board Top)
Board Reference
Board Label
Description
J8 pins 1-2
1.35V
1.35 V FMCB V
CCIO
select
J8 pins 3-4
1.5V
1.5 V FMCB V
CCIO
select
J8 pins 5-6
1.8V
1.8 V FMCB V
CCIO
select
J11 pins 1-2
1.35V
1.35 V FMCA V
CCIO
select
UG-01170
2015.06.26
Default Switch and Jumper Settings
3-3
Development Board Setup
Altera Corporation
