Several designs are provided to test the major board features. Each design provides data for one or more
tabs in the application. The Configure menu identifies the appropriate design to download to the FPGA
for each tab.
After successful FPGA configuration, the appropriate tab appears that allows you to exercise the related
board features. Highlights appear in the board picture around the corresponding components
The BTS communicates over the JTAG bus to a test design running in the FPGA. The Board Test System
and Power Monitor share the JTAG bus with other applications like the Nios II debugger and the
SignalTap
®
II Embedded Logic Analyzer. Because the Quartus II programmer uses most of the bandwidth
of the JTAG bus, other applications using the JTAG bus might time out. Be sure to close the other applica‐
tions before attempting to reconfigure the FPGA using the Quartus II Programmer.
Preparing the Board
With the power to the board off, follow these steps:
1. Connect the USB cable to your PC and the board.
2. Ensure that the Ethernet patch cord is plugged into the RJ-45 connector.
3. Check the development board switches and jumpers are set according to your preferences. See the
“Factory Default Switch and Jumper Settings” section.
4. Set the load selector switch (SW6.4) to OFF for user hardware1 (page #1).
The development board ships with the CFI flash device preprogrammed with a default:
• Factory FPGA configuration for running the Board Update Portal design example
• User configuration for running the Board Test System demonstration
5. Turn on the power to the board. The board loads the design stored in the user hardware1 portion of
flash memory into the FPGA. If your board is still in the factory configuration, or if you have
downloaded a newer version of the Board Test System to flash memory through the Board Update
Portal, the design loads the GPIO, Ethernet, and flash memory tests.
To ensure operating stability, keep the USB cable connected and the board powered on when running
the demonstration application. The application cannot run correctly unless the USB cable is attached
and the board is on.
Related Information
Default Switch and Jumper Settings
on page 3-2
Running the Board Test System
To run the Board Test System (BTS), navigate to the
<install dir> \kits\<device name>\examples\board_test_
system
directory and run the
BoardTestSystem(32-bit).exe or BoardTestSystem(64-bit).exe
application.
On Windows, you can also run the BTS from the Start > All Programs > Altera menu.
A GUI appears, displaying the application tab that corresponds to the design running in the FPGA. The
development board’s flash memory ships preconfigured with the design that corresponds to the GPIO tab.
4-2
Preparing the Board
UG-01170
2015.06.26
Altera Corporation
Board Test System
