Alpha Data ADM-SDEV-CFG1, Руководство пользователя

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ADM-SDEV-CFG1 User Manual
V1.2 - 18th March 2020
3.3 Clocks
The ADM-SDEV-CFG1 board can provide two different clock sources to the Base board FPGA.
One clock source is generated by an on board oscillator and the other can be input via connector J4.
Source Signal Frequency FPGA Input
IO
Standard
"P" pin "N" pin
External (J5) CLK2_M2C_0 Variable Bank 24 LVDS AM32 AN32
Oscillator CLK2_M2C_1 150MHz Fixed Bank 24 LVDS AM31 AN31
Table 3 : Input CLK_M2C Connections
The ADM-SDEV-CFG1 board can also output a clock signal via connector J4.
This clock is generated by the FPGA on the base board.
Source Signal Frequency FPGA Input
IO
Standard
"P" pin "N" pin
FPGA DP1_C2M_1 Variable MGT Quad 224 LVDS AV6 AV5
Table 4 : Output Clock Connection
3.4 IPASS Connector
One of the high speed serial lanes is connected to an IPASS connector for remote PCIe connection.
Connector Signal FPGA Bank "P" pin "N" pin
IPASS (J6)
DP0_C2M MGT Quad 224 AW8 AW7
DP0_M2C MGT Quad 224 AW4 AW3
GBTCLK0_M2C MGT Quad 224 AT10 AT9
Table 5 : IPASS PCIe Connections
3.5 SATA Connectors
The ADM-SDEV-CFG1 board has two standard right angle SATA receptacles for use with SATA compliant
storage devices.
Connector Signal FPGA Bank "P" pin "N" pin
SATA_1 (J7)
DP2_C2M MGT Quad 224 AU8 AU7
DP2_M2C MGT Quad 224 AU4 AU3
SATA_2 (J8)
DP3_C2M MGT Quad 224 A16 A15
DP3_M2C MGT Quad 224 A12 A11
Table 6 : SATA Connections
3.6 Health Monitoring
The ADM-SDEV-BASE has the ability to monitor temperature and voltage to maintain a check on the operation
of the board. The monitoring is implemented using the Atmel AVR microcontroller.
The system monitor microcontroller can be accessed via the USB connector (J3), please refer to the
Page 6 Functional Description
ad-ug-1361_v1_2.pdf