Alpha Data ADM-SDEV-CFG1, Руководство пользователя

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ADM-SDEV-CFG1 User Manual
V1.2 - 18th March 2020
Comp. Ref. Function ON State Off State
D1(Green)
3.3V Supply
Status
Normal operation Power Off
Table 2 : LED Definitions
3.2 JTAG Interface
3.2.1 On-board Interface
The JTAG boundary scan chain can be accessed via a standard header (J2).
This allows the connection of the Xilinx JTAG cable for FPGA debug and QSPI Flash programming via the Xilinx
toolchain.
The JTAG chain starts on the config FMC board and through the Base board, passing through the FPGA, the
LPC FMC (if fitted) and the FMC+ (if fitted).
The scan chain is shown in JTAG Boundary Scan Chain :
FPGA
XCKU060
LPC
FMC
(J1)
FMC1_PRESENT#
Level Shift
FMC2_VIO –> 3V3
En#
FMC1_TDI
FMC1_TDO
FPGA_TDI
HDR_TDO
Level Shift
3V3 -> FMC2_VIO
FMC2_TDI
FMC2_TDO
Config
FMC
(J2)
FMC+
(J3)
FMC3_PRESENT#
Level Shift
FMC2_VIO –> 3V3
En#
FMC3_TDI
FMC3_TDO
FPGA_TDO
Figure 4 : JTAG Boundary Scan Chain
3.2.2 JTAG Voltages
The Vcc supply provided to the JTAG cable on the config header is +3.3V and is protected by a poly fuse rated at
375mA.
The voltage level of the JTAG chain on the ADM-SDEV-BASE board is set to the config FMC adjustable voltage
FMC2_VIO.
Page 5 Functional Description
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