ADM-PA101 User Manual
3.2.1 Si5328
If jitter attenuation is required please see the reference documentation for the Si5328.
www.silabs.com/Support%20Documents/TechnicalDocs/Si5328.pdf
There are two input clock options. Si5328 pin CLKIN1 (board net name SI5328_REFCLK_IN_P/N) of the Si5328
is connected to an MGT clock output for the most direct clock recovery architecture. Si5328 pin CLKIN2 (board
net name MGT_PROGCLK_6_P/N) of the Si5328 is connected to a programable clock from the onboard clock
synthesizer.
The two output clocks are connected to quads 201 and 204 to provide clocking capability to the entire FMC+
interface.
The INT_C1B and LOL signals for the Si5328 is available for use, and can be located at net names
SI5328_1V5_INT_C1B and SI5328_1V5_LOL in the
.
The active low reset of the Si5328 is accessible to the ACAP. See net names SI5328_1V5_RST_L in the
Note:
Each sideband signal has an external pull-up resistor.
The Si5328 configuration register map is volatile, and must be written on each power up event over I2C. Use
nets SI5328_1V5_SDA and SI5328_1V5_SCL at pins located in the
. The Si5328 device
is configured the I2C address shown in the table below:
device
7bit Hex Address
Binary Address
Si5328
68
110_1000
Table 5 : Si5328 address table
3.2.2 PCIe Reference Clocks
The 16 MGT lanes connected to the PCIe card edge use MGT tiles 103 through 106 and use the host system's
100 MHz PCIe reference clock (net name PCIE_REFCLK_0_P/N or PCIE_REFCLK_1_P/N in the
Alternatively, a more stable but asynchronous onboard 100MHz clock is available as well (net name
PCIE_LCL_REFCLK_P/N in the
3.2.3 Fabric Clock
The design offers a fabric clock (net name FABRIC_CLK_P/N) which defaults to 300 MHz. This clock is intended
to be used for IDELAY elements in PL designs. The fabric clock is connected to a Global Clock (GC) pin. This
clock frequency can be changed to any arbitrary clock frequency up to 350MHz by re-programing the Si5338
reprogrammable clock oscillator. See details on avr2util in the section:
Use constraints DIFF_TERM_ADV = TERM_100 and IOSTANDARD LVDS15 for this reference clock.
See net names FABRIC_CLK_P/N in the
for pin locations.
3.2.4 PS Reference Clock (PS_REF_CLK)
A 50MHz clock is fed into the dedicated REF_CLK_503 pin to drive the processor system.
3.2.5 MGT Programable Clock
The MGT reference clock connects to each quad connected to the FMC connector, the Si5328, and the FireFly
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Functional Description
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