Alesis MIDIVERB IV, Руководство по обслуживанию

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Alesis MidiVerb IV Service Manual‘ 3 03/05/99
5.00 Digital Signal Paths
The 80C31 MPU (U14) controls all "user interface" functions of the M4. These functions
range from handling the front panel buttons, to continuously updating algorithm information to
the M4 ASIC (U9). Note that the 8031 data buss serves a dual purpose. This buss multiplexes
between low order addresses (1st 8 bits), and data. A latch contained in the M4 ASIC is used to
hold the low order address half, during 8031 read and write cycles. The EPROM (U2) is used to
hold both program information, and algorithm data. The SRAM (U10) holds system variables, as
well as user preset data. MIDI I/O is handled through the 8031’s built in RXD (Read Serial
Data), and TXD (Transmit Serial Data) ports. Front panel keypad decoding and DigPot control
are handled through the 8031’s built in I/O ports.
5.10 RESET
The 8031 reset circuit is perhaps the single most important circuit in the M4. When this
circuit is functioning incorrectly, a complete lock-up of the machine, will occur.
On power up, the 2N4401 transistor is off (the raw supply hasn’t raised up far enough yet
to bias the transistor on, through R5, R8, and the zener divider network). The rest of the circuit
is contained within the M4 ASIC. When the raw supply reaches approximately 7 volts, the
transistor will turn on, causing the reset line to drop low. The opposite should occur on power
down (transistor turns off at 7V threshold, reset line goes high during the discharge of the power
rails) ensuring data integrity.
5.20 M4 ASIC
A full discussion of this device is beyond the scope of this manual, however a brief
description of the important pins is necessary, and presented below.
PIn #(s) Function
53
SRAMCE> SRAM Chip Enable - Enable line for 8031 SRAM.
55 PUPIN> Power UP IN - Conditioned raw +5V is used to determine the
time at which the unit resets. Reset will not occur until the raw supply
reaches approximately 7V. This is done to ensure that the regulated
+5 is steady before machine operation can begin.
56
PUPOUT> Power UP OUT - Basically the reset out line.
1-4, 61-64 MICROAD0-7>
MICROprocessor ADdress 0-7 - Because the 8031
data buss is multiplexed between data and low order addresses, a
latch must be provided external to hold the low order half of the
address during data transfers. This latch (which was a discreet
component in earlier Alesis products) has now been incorporated into
the M4 ASIC. (See also MICROALE, LSADDR0-7.)
5, 6 MICROAD12, 15>
MICROprocessor ADdress 12,15 - These two
address lines from the 8031 are used to decode memory mapped
locations such as the LCD enable.
7
MICRORD> MICROprocessor ReaD enable-
8 MICROWR>
MICROprocessor WRite enable-