Albalá Ingenieros IPA3000C01, Руководство пользователя

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Albalá Ingenieros | Manual IPA3000C01
TX_COL_DELAY 0x00 0x77 0xFF Y N FEC column delay
= x
LOW_COST 0x00 0x88 0x02 Y N TOS. Low cost
0=No, 1=Yes
HIGH_RELIABILTY 0x00 0x88 0x04 Y N TOS. High reliability
0=No, 1=Yes
HIGH_THROUGHPUT 0x00 0x88 0x08 Y N TOS. High Throughput
0=No, 1=Yes
LOW_DELAY 0x00 0x88 0x10 Y N TOS. Low delay
0=No, 1=Yes
PRECEDENCE 0x00 0x88 0xE0 Y N TOS. Precedence
0=Routine, 1=Priority, 2=Inmediate, 3=Flash, 4=Flash override, 5=Critic/ECP,
6=Internetwork control,7=Network control
TTL 0x00 0x89 0xFF Y N Time to live
= x
STR1_IGM_F_ADD_3 0x00 0xA0 0xFF Y N Source IP address (3) (IP main RX)
= x
STR1_IGM_F_ADD_2 0x00 0xA1 0xFF Y N Source IP address (2) (IP main RX)
= x
STR1_IGM_F_ADD_1 0x00 0xA2 0xFF Y N Source IP address (1) (IP main RX)
= x
STR1_IGM_F_ADD_0 0x00 0xA3 0xFF Y N Source IP address (0) (IP main RX)
= x
STR2_IGM_F_ADD_3 0x00 0xA4 0xFF Y N Source IP address (3) (IP reserve RX)
= x
STR2_IGM_F_ADD_2 0x00 0xA5 0xFF Y N Source IP address (2) (IP reserve RX)
= x
STR2_IGM_F_ADD_1 0x00 0xA6 0xFF Y N Source IP address (1) (IP reserve RX)
= x
STR2_IGM_F_ADD_0 0x00 0xA7 0xFF Y N Source IP address (0) (IP reserve RX)
= x
STATUS
Name add ext msk snmp trap Description
1PPS_FAIL 0x01 0x01 Y Y 1PPS reference input status
0=OK,1=Fail
10MHZ_FAIL 0x01 0x02 Y Y 10MHz reference input status
0=OK,1=Fail
OUTPUT_FAIL 0x01 0x08 Y Y The output signal is not valid because all inputs failed
0=OK,1=Fail
ASI_MAIN_DEL_WAR 0x01 0x10 Y Y The ASI main delay is greater than the programmed output delay
0=OK,1=Fail
ASI_RES_DEL_WAR 0x01 0x20 Y Y The ASI reserve delay is greater than the programmed output delay
0=OK,1=Fail
IP_MAIN_DEL_WAR 0x01 0x40 Y Y The IP main delay is greater than the programmed output delay
0=OK,1=Fail
IP_RES_DEL_WAR 0x01 0x80 Y Y The IP reserve delay is greater than the programmed output delay
0=OK,1=Fail
ASI_MAIN_FAIL 0x02 0x01 Y Y ASI main input status
0=OK,1=Fail
EX_ASI_MAIN_FAIL 0x02 0x02 Y Y ASI main external input fail status
0=OK,1=Fail
ASI_RES_FAIL 0x02 0x04 Y Y ASI reserve input status
0=OK,1=Fail
EX_ASI_RES_FAIL 0x02 0x08 Y Y ASI reserve external input fail status
0=OK,1=Fail
IP_MAIN_FAIL 0x02 0x10 Y Y IP main input status
0=OK,1=Fail
EX_IP_MAIN_FAIL 0x02 0x20 Y Y IP main external input fail status
0=OK,1=Fail
IP_RES_FAIL 0x02 0x40 Y Y IP reserve input status
0=OK,1=Fail
EX_IP_RES_FAIL 0x02 0x80 Y Y IP reserve external input fail status
0=OK,1=Fail
ASIM_ASIR_SEAM 0x03 0x01 Y N ASI main to ASI reserve seamles switching capability
0=Seamless, 1=No seamless
ASIM_IPM_SEAM 0x03 0x02 Y N ASI main to IP main seamles switching capability
0=Seamless, 1=No seamless
ASIM_IPR_SEAM 0x03 0x04 Y N ASI main to IP reserve seamles switching capability
0=Seamless, 1=No seamless
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