Alan HM135, Руководство по обслуживанию

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HM135 Service Manual
Preliminary version Page 6 of 13
2.4.c Synthesizer
The PLL IC frequency synthesizer is a large scale monolithic synthesizer integrated circuit DA3 .
The synthesizer IC contains a dual modular prescaler, programmable divide-by-N counter, prescaler control
(swallow) counter, reference divider, phase detector and unlock detector.
RF output from the active VCO is AC coupled to the synthesizer DA3 prescaler input at Pin 8 . The divide-by-N
counter chain in DA3 , consisting of the dual-modulus prescaler, swallow counter and programmable counter,
divides the VCO signal down to a frequency very close to 5.00 KHz or 6.25 KHz which is applied to the phase
detector. The phase comparator compares the edges of this of this signal with that of the 5.00 KHz or 6.25 KHz
reference signal from the reference divider and drives the external charge pump (
VT12 , VT13 , VT14 and VT15 ).
The synthesizer unlock detector circuit prevents the operation of the transmitter when the phase lock loop (PLL) is
unlocked. The following discussion assumes the unit has been placed in the transmit mode.
DA3 lock detector Pin
7 goes high when the PLL is properly locked. This high level is applied to pin 21 of the microprocessor DD5 . A
software timing routing brings the pin 28 of the microprocessor DD5 low making the line PA (connected via R323
and C361 ) low as well. With the PA line low, VT28 is cut off and VT27 biases the RF driver (VT23) and RF power
amplifier ( VT22 ) which enables transmission.
When the PLL become unlocked, the lock detector at DA3 pin 7 will begin pulsing low. A RC circuit ( R311 and
C347 ) converts pulsing low to a low level for the microprocessor (pin 21 ). The microprocessor then changes the
PA line to a high switching the transistor VT28 on. This cuts off the transistor VT27 which is not able to supply the
bias to the RF driver and RF power amplifier disabling the transmission. Therefore, the transmitter remains
disabled while the phase locked loop remains unlocked.
2.5 Transmitter
2.5.a RF Power Amplifier
The TX RF amplifier is made with 3 stages: VT24 is the pre-driver, VT23 is the driver and VT22 is the Power
Amplifier (PA). Output from the last PLL buffer DA5 (line HET_TX ) feeds the pre-driver amplifier VT24 . The output
signal from VT24 feeds the driver amplifier VT23 , whose output from the driver stage feeds the final RF power
amplifier VT22 to produce the rated output power of 25 watts. The output of the power amplifier is applied to the
RX/TX switch made with VD21 , VD22 and related circuitry, then to the low-pass filter (consisting of L46 to L49
and connected capacitors) and then to the SWR coupling line TA1 which is directly connected to the antenna
connector.
The 8V_TX_F line supplies the total bias current to the bias regulators. Pre-driver is biased by VT25 and both the
driver and power amplifier are biased by the same transistor VT27 . Obviously, the output of VT27 biases these
two stages via 2 different trimmers, which are RP5 for the driver (about 200 mA) and RP6 for the power amplifier
(about 300mA).
2.5.b Antenna Switching
Switching of the antenna between the transmitter and the receiver is accomplished by the antenna
transmit/receive switch consisting of diodes
VD21 and VD22 in conjunction with C189 , C190 and L44 . In reception
mode both the diodes are unbiased, so the RX signal coming from the ANTENNA line passes through the
coupling line TA1 , the low pass filter ( L49 , L48 , L46 , C193 , C194 etc.), going to the receiver’s front-end input (line
RF_RX ) via L144 . In the transmit mode, switched +8VTX is applied to the base of VT26 through R142 and R143
hard forward biasing the two diodes on. VD21 thus permits the RF power from output of the power amplifier to
flow to the input of the low-pass filter. At the same time, VD22 avoids that the residual RF coming from the
transmitter is accidentally sent to the receiver by removing it with the 3 capacitors C183 , C184 and C185 .
2.5.c Power control
Output power is picked up from the output coupling line TA1 and sent to the diodes VD24 and VD26 . The first one
detects the forward power and the second one the reflected power which drops, respectively, across R145 and
R156 . These two signals (respectively the lines FWD_PWR and REFL_PWR ) are fed separately to an operational
amplifier ( DA6:A and DA6:B ) and combined into a third one ( DA6:C ) which regulated the output power according
to the input signal. The calibration of the output power is provided by the trimmer RP7 which controls DA6:C . Its
output is connected to the transistor VT27 which provides the bias for the driver and power amplifier closing the
power control loop. In case of excessive S.W.R., the output power is automatically reduced in order to protect the
final stage.