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[AKD4753-A]
4) PLL Master Mode
(a)
All interface signals including master clock are fed externally.
(a-1) Setup the MCKI.
X1(X’Tal) or J7(MCKI) are used. Nothing should be connected to PORT1(RX).
(a) When using X1(X’Tal) (b) When using J7(MCKI)
JP7
AK4753-MCLK
MC
K
I
DI
R
EX
T
JP3
XT
L
EX
T
GN
D
JP7
AK4753-MCLK
MC
K
I
DI
R
EXT
JP3
XT
L
EX
T
GN
D
Figure 7. Setup the MCKI
(a-2) Other Setting (BICK, LRCK and SDATA).
PORT3(DSP) is used. Nothing should be connected to PORT1(RX).
EXT
DIR
JP4
AK4753-BICK
JP5
AK4753-SDATA
JP6
AK4753-LRCK
EXT
DIR
EXT
DIR
JP17
MODE_SEL
SLAVE
MASTER
JP18
MCLK_SEL
MCLK
MUTEN
Figure 8. Other Setting (BICK, LRCK and SDATA)
KM103902
2011/01
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