AKM AKD4552-A, Руководство пользователя, Страница: 8 / 33

ASAHI KASEI [AKD4552-A]
<KM080600> 2005/10
- 8 -
(6) All interface signals including master clock are fed externally.
Under the following set-up, all external signals needed for the AK4552 to operate could be fed through PORT3
(ROM). In case of interfacing external sources to D/A converter, JP6 (SDTI) should be open. And in case of
using A/D data to externally, JP6 (SDTI) is set ADC side. When JP6 (SDTI) is open, the A/D data can be output
from the SDTO pin of PORT3 (ROM) at the same time if JP5 (SDTO) is short.
JP3
LRCK
DIR ADC
JP4
BCLK
JP8
XTE
JP13
DIR ADC
JP6
SDTI
DIR ADC
EXT
•
Clock example
6-1) Normal speed, Double speed, 4 times speed of ADC and DAC
Do not use X2.
JP2
MCKO
M2 M1
JP7
SPEED
JP9
MCLK
X2 X1 X4 X1
X4
X2
X1
X4 X1
JP10
BCFS
JP12
LRFS
JP11
CLK
DIR
EXT
XTL
SW2
MODE
1 2 3 4 5
DE
M0
DE
M1
OCK
S
0
OCK
S
1
CM
0
H
L
L
L L
„
DIP switch set up
Upper-side is “H” and lower-side is “L”.
[SW2] (MODE) : Sets the de-emphasis filter of AK4552 and clock mode of U4 (AK4112B).
No. Pin Name Mode
1 DEM0
2 DEM1
See Table 2.
3 OCKS0
4 OCKS1
See Table 3.
5 CM0 L : X’tal mode, H : PLL mode
Table 1. Set up SW2
DEM1 DEM0 Mode
L L 44.1kHz
L H OFF
H L 48kHz
H H 32kHz
default
Table 2. Set up of DEM0/1 of AK4552
No. OCKS1 OCKS0 MCKO1 MCKO2 fs (kHz)
0 L L 256fs 256fs 32, 44.1, 48, 96
1 H L 512fs 128fs 32, 44.1, 48
Table 3. Set up of OCKS0/1 for AK4112B