
ASAHI KASEI
[AKD4552-A]
<KM080600>
2005/10
-
7
-
(5) Evaluation of A/D using D/A converted data
It is possible to make evaluation in the form of analog inputs and analog outputs by interfacing with various
AKM’s D/A evaluation boards with PORT3 (ROM). Nothing should be connected to PORT1 (DIR).
JP3
LRCK
DIR
ADC
JP4
BCLK
JP8
XTE
JP13
DIR
ADC
JP6
SDTI
DIR
ADC
EXT
•
Clock example
5-1) Normal speed of ADC (MCLK=256fs)
Do not use X2.
JP2
MCKO
M2
M1
JP7
SPEED
JP9
MCLK
X2
X1
X4
X1
X4
X2
X1
X4
X1
JP10
BCFS
JP12
LRFS
JP11
CLK
DIR
EXT
XTL
5-2) Normal speed of ADC (MCLK=512fs)
Do not use X2.
JP2
MCKO
M2
M1
JP7
SPEED
JP9
MCLK
X2
X1
X4
X1
X4
X2
X1
X4
X1
JP10
BCFS
JP12
LRFS
JP11
CLK
DIR
EXT
XTL