Aiwa XP-ZR850, Руководство по обслуживанию

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XP-ZR850
XP-ZR850
SECTION 5
DIAGRAMS
Note on Printed Wiring Boards.
•
X : parts extracted from the component side.
•
Y
: parts extracted from the conductor side.
• z : Through hole.
•
W
: indicates side identified with part number.
• f : internal component
• : Pattern from the side which enables seeing.
(The other layers' patterns are not indicated.)
• Note for Printed Wiring Boards and Schematic Diagrams
Caution:
Pattern face side:
Parts on the pattern face side seen from
(Conductor Side) the pattern face are indicated.
Parts face side: Parts on the parts face side seen from
(Component Side) the parts face are indicated.
• EGL board is multi-layer printed board.
However, the patterns of intermediate-layer have not been in-
cluded in the diagram.
Note on Schematic Diagrams.
• All capacitors are in
µ
F unless otherwise noted. (p: pF)
50 WV or less are not indicated except for electrolytics
and tantalums.
• All resistors are in
Ω
and 1 /
4
W or less unless otherwise
specified.
• f : internal tolerance.
•
C
: panel designation.
•
A
: B+ Line.
• H : adjustment for repair.
• Power voltage is dc 1.5 V and fed with regulated dc power
supply from battery terminal.
• Voltages and waveforms are dc with respect to ground
under no-signal (detuned) conditions.
no mark : CD PLAY
( ) : FM
[ ] : AM
• Voltages are taken with a VOM (Input impedance 10 M
Ω
).
Voltage variations may be noted due to normal produc-
tion tolerances.
• Waveforms are taken with a oscilloscope.
Voltage variations may be noted due to normal produc-
tion tolerances.
• Circled numbers refer to waveforms.
• Signal path.
J
: CD PLAY
F
: FM
f
: AM
• The voltage and waveform of CSP (chip size package)
cannot be measured, because its lead layout is different
from that conventional IC.
• Abbreviation
E/4 : Argentina model
E19 : South African, Singapore, Malaysia, Vietnam
and Indian model
E92 : Panama, Venezuelan and Caribbian Can model
MX : Mexican model
Caution:
Pattern face side:
Parts on the pattern face side seen from
(Side B) the pattern face are indicated.
Parts face side: Parts on the parts face side seen from
(Side A) the parts face are indicated.
• Lead Layouts
Lead layout of conventional IC CSP (chip size package)
surface
– EGL Board – – JACK Board –
1
X602
500 mV/DIV, 20 n s/DIV
45.5 ns
1.1 Vp-p
qs
Q104 (Collector) (FM mode)
1 V/DIV, 50
n
s/DIV
195 ns
2.2 Vp-p
qs
Q104 (Collector) (AM mode)
500 mV/DIV, 50
n
s/DIV
195 ns
1.2 Vp-p
qa
IC101
qg
(X_0) (FM mode)
1 V/DIV, 5
µ
s/DIV
13.3
µ
s
1.6 Vp-p
qa
IC101
qg
(X_0) (AM mode)
200 mV/DIV, 5
µ
s/DIV
13.3
µ
s
0.5 Vp-p
qd
IC401
wd
(SYNC)
(CD play mode)
1 V/DIV, 1
µ
s/DIV
2.8
µ
s
2.1 Vp-p
2.8
µ
s
2.7 Vp-p
qf
IC401
ta
(LO_2),
ts
(LO_1)
1 V/DIV, 1
µ
s/DIV
• Waverforms
Note: The components identified by mark
0
or dotted
line with mark
0
are critical for safety.
Replace only with part number specified.
Ver. 1.2