Aiwa XP-V320, Руководство по обслуживанию

Страница: 17 / 30

-17-
Pin No. Pin Name I/O Description
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
Digital OUT output pin. (EIAJ format) (Not connected)
Output pin for the 7.35kHz synchronization signal divided from the crystal osillator. (Not
connected)
(Not connected)
C1 C2 error correction monitor pin. Test input pin. Must be connected to OV.
Emphasis pin. Which becomes an input pin after reset and can becontrolled externally. This
becomes an emphasis monitor pin under control by command. (Not connected)
L channnel mute output pin. (Not connected)
R channel mute output pin. (Not connected)
L channel power supply pin. (2000pF or more path controller to be inserted at a point nearer to
the pin between this pin and GND)
L channel output pin.
L channel ground pin, Must be connected to 0V.
R channel ground pin, Must be connected to 0V.
R channel output pin.
R channel power supply pin. (2000pF or more path controller to be inserted at a point nearer to
the pin between this pin and GND)
Crystal oscillator power supply pin. (2000pF or more path controller to be inserted at a point
nearer to the pin between this pin and GND)
Connections for a 16.9344MHz crystal oscillator pin.
Crystal oscillator ground pin. Must be connected to 0V.
L/R clock input pin. (Must be connected to 0V when unused)
Bit clock input pin. (Must be connected to 0V when unused)
L/R channel data input pin. (Must be connected to 0V when unused)
L/R clock output pin.
Bit clock output pin. (Not connected)
L/R channel data output pin. (Not connected)
16.9344MHz output pin. (Not connected)
Subcode frame synchronization signal output pin. This signal falls when the subcode is in the
standby state. (Not connected)
Subcode clock synchronization signal output pin. (Not connected)
Subcode P, Q, R, S, T, U and W output pin. (Not connected)
Subcode readout clock input pin.
Chip enable signal input pin.
Data transfer clock input pin.
Data input pin.
Data output pin.
Interruption signal output pin. (Not connected)
Interruption signal output pin.
Reset input pin. This pin must be set low briefly after power is first applied.
DOUT
FSX
EFLG
TEST
EMPH
MUTEL
MUTER
LVDD
LCHO
LVSS
RVSS
RCHO
RVDD
XVDD
XIN
XOUT
XVSS
ASLRCK
ASDACK
ASDFIN
LRSY
DATACK
DATA
16M
SFSY
SBSY
PW
SBCK
CE
CL
DI
DO
INT
WRQ
RES
O
O
O
I
I/O
O
O
—
O
—
—
O
—
—
I
O
—
I
I
I
O
O
O
O
O
O
O
I
I
I
I
O
O
O
I
IC DESCRIPTION-1/3 (LC78641NE-D)-2/3