Aiwa XP-SR320, Руководство по обслуживанию

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Pin No. Pin Name I/O Description
49 AVSS1 I Analogue circuit GND.
50 OUTR O Rch audio output.
51 AVDD1 I Analogue circuit power.
52 FSEL I Noise filter ON/OFF switch input. “L” = ON, “H” = OFF. (Connected to VDD)
53 TMOD1 I Terminal mode switch input terminal 1. Normally set to “L”. (Connected to GND)
54 TMOD2 I Terminal mode switch input terminal 2. Normally set to “L”. (Connected to GND)
55 FLAG O Flag signal output. (Not used)
Command switch: Spindle servo phase synchronizing signal output.
56 CLVS/IPFLAG O “H” = CLV, “L” = Rough servo.
Interpolation flag signal output. “H” = Interpolation. (Not used)
57 EXT0 I/O Command switch: Extension input/output port 0, SRDATA input. (Not used)
58 EXT1 I/O
Command switch: Extension input/output port 1, LRCK input.
“H” = Lch audio data, “L” = Rch audio data. (Not used)
59 EXT2 I/O Command switch: Extension input/output port 2, BCLK input. (Not used)
60 TX O Digital audio interface output signal. (Not used)
61 MCLK I Microcomputer command clock signal input. (Data is latched at loading edge)
62 MDATA I Microcomputer command data signal input.
63 MLD I Microcomputer command load signal input. “L” = Load.
64 BLKCK O Sub-code block clock signal fBLKCK = 75 Hz. (In normal PLAY mode)
65 SQCK/BCLK I/O Command switch: Sub-code Q resistor external clock input, SRDATA bit clock output. (Not used)
66 SUBQ/LRCK O
Command switch: Sub-code Q data output, L, R discrimination signal output.
“H” = Lch audio data, “L” = Rch audio data. (Not used)
67 DMUTE/SRDATA I/O Command switch: Muting input, “H” = MUTE. Serial data output. (Connected to GND)
Status signal (CRC, RESY, CLVS, NTTSTOP, SQOK, FLAG6, SENSE,NFLOCK
68 STAT O NTLOCK, BSSEL, SUBQ DATA, CDTEXT DATA, SHOCK RESISTANCE READ
DATA).
69 NRST I Reset input. “L” = Reset.
70 SPPOL O Spindle motor drive signal output. (Polar output)
71 PMCK O 88.2 kHz clock signal output. (Not uesed)
72 SMCK O 4.2336 MHz clock signal output.
73 SUBC/SSYNC O Command switch: Sub-code serial output, Sector SYNC output. (Not used)
74 SBCK/64FS I Command switch: Clock input for sub-code serial output, 64FS output. (Not used)
75 NCLDCK O Sub-code frame clock signal output. (fCLDCK = 7.35 kHz) (Not used)
76 NTEST I Test terminal, normally set to “H”. (Connected to VDD)
77 X1 I Quartz oscillator circuit input terminal f = 16.93 MHz.
78 X2 O Quartz oscillator circuit output terminal f = 16.93 MHz.
79 DVDD1 I Digital circuit power.
80 DVSS1 I Digital circuit GND.
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