Aiwa XP-SR320, Руководство по обслуживанию

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Pin No. Pin Name I/O Description
1 DVDD3 I DRAM interface power (terminal No. 2 to 19).
2 ~ 3 D0 ~ D1 I/O DRAM data input/output signal 0 ~ 1.
4 NWE O DRAM write enable signal.
5 NRAS O DRAM RAS control signal.
6 ~ 7 D2 ~ D3 I/O DRAM data input/output signal 2 ~ 3.
8 NCAS0 O DRAM CAS control signal 0.
9 A10 O DRAM address signal 10.
10 ~ 14 A8 ~ A4 O DRAM address signal 8 ~ 4.
15 A9 O DRAM address signal 9.
16 ~ 19 A0 ~ A3 O DRAM address signal 0 ~ 3.
20 DVSS2 I Digital circuit GND.
21 DVDD2 I Digital circuit power.
22 SPOUT O Spindle motor driver signal output.
23 TRVM O Traverse drive output (+ polar output).
24 TRVP O Traverse drive output (- polar output).
25 TRM O Tracking drive output (+ polar output).
26 TRP O Tracking drive output (- polar output).
27 FOM O Focus drive output (+ polar output).
28 FOP O Focus drive output (- polar output).
29 FBAL O Focus balance adjustment output.
30 TBAL O Tracking balance adjustment output.
Specified crystal oscillation frequency signal input. (Connected to GND)
31 CSEL I “H” : Crystal oscillation fregnency = 33.8688MHz.
“L” : Crystal oscillation fregnency = 16.9344MHz.
32 FE I Focus error signal input (analogue input).
33 TE I Tracking error signal input (analogue input).
34 RFENV I RF envelope signal input (analogue input).
35 OFT I Off track signal input. “H” = Off track.
36 NRFDET I RF detection signal input. “L” = Detected.
37 BDO I Drop out signal input. “H” = Drop out.
38 LDON O Laser ON signal output. “H” = ON. (Not used)
39 ARF I RF signal input.
40 IREF I Reference current input terminal.
41 ADPVCC I AD reference voltage input (analogue input).
42 DSLF O DSL loop filter terminal.
43 DRF O Bias terminal for DSL.
44 PLLF O PLL loop filter terminal.
45 VCOF O Jitter free VCO loop filter terminal.
46 AVDD2 I Analogue circuit power (for DSL, PLL, VCOF, AD, DA).
47 AVSS2 I Analogue circuit GND (for DSL, PLL, VCOF, AD, DA).
48 OUTL O Lch audio output.
IC, MN35530
IC DESCRIPTION
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